UART code written in VHDL, experience card features a very wide.

uart
....\baudrate_generator.vhd
....\baudrate_generator_TB.vhd
....\counter.vhd
....\counter_TB.vhd
....\db
....\..\prev_cmp_uart.map.qmsg
....\..\uart.asm.qmsg
....\..\uart.asm_labs.ddb
....\..\uart.cbx.xml
....\..\uart.cmp.cdb
....\..\uart.cmp.hdb
....\..\uart.cmp.logdb
....\..\uart.cmp.rdb
....\..\uart.cmp.tdb
....\..\uart.cmp0.ddb
....\..\uart.dbp
....\..\uart.db_info
....\..\uart.eco.cdb
....\..\uart.fit.qmsg
....\..\uart.hier_info
....\..\uart.hif
....\..\uart.map.cdb
....\..\uart.map.hdb
....\..\uart.map.logdb
....\..\uart.map.qmsg
....\..\uart.pre_map.cdb
....\..\uart.pre_map.hdb
....\..\uart.psp
....\..\uart.pss
....\..\uart.rtlv.hdb
....\..\uart.rtlv_sg.cdb
....\..\uart.rtlv_sg_swap.cdb
....\..\uart.sgdiff.cdb
....\..\uart.sgdiff.hdb
....\..\uart.signalprobe.cdb
....\..\uart.sld_design_entry.sci
....\..\uart.sld_design_entry_dsc.sci
....\..\uart.smp_dump.txt
....\..\uart.syn_hier_info
....\..\uart.tan.qmsg
....\detector.vhd
....\detector_TB.vhd
....\parity_verifier.vhd
....\parity_verifier_TB.vhd
....\prev_cmp_uart.qmsg
....\shift_register.vhd
....\shift_register_TB.vhd
....\switch.vhd
....\switch_bus.vhd
....\switch_bus_TB.vhd
....\uart.asm.rpt
....\uart.done
....\uart.fit.rpt
....\uart.fit.smsg
....\uart.fit.summary
....\uart.flow.rpt
....\uart.map.rpt
....\uart.map.summary
....\uart.pin
....\uart.pof
....\uart.qpf
....\uart.qsf
....\uart.qws
....\uart.tan.rpt
....\uart.tan.summary
....\uart_core.vhd
....\uart_description.txt
....\UART_PACKAGE.vhd
....\uart_top.vhd
....\uart_top_tb.vhd

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