Using Verilog to achieve the first commercial cryptographic algorithm for encryption and decryption SMS4.

SMS4_code
.........\BK_SHIFT0
.........\BK_SHIFT0.v
.........\BK_SHIFT0.v.bak
.........\BK_SHIFT1
.........\BK_SHIFT1.v
.........\BK_SHIFT1.v.bak
.........\BK_SHIFT2
.........\BK_SHIFT2.v
.........\BK_SHIFT2.v.bak
.........\B_SHIFT0.v
.........\B_SHIFT0.v.bak
.........\B_SHIFT1.v
.........\B_SHIFT1.v.bak
.........\B_SHIFT2.v
.........\B_SHIFT2.v.bak
.........\B_SHIFT3.v
.........\B_SHIFT3.v.bak
.........\B_SHIFT4.v
.........\B_SHIFT4.v.bak
.........\CK.v
.........\CK.v.bak
.........\de_reference_result.v
.........\de_reference_result.v.bak
.........\edcrypt_ori.v
.........\edcrypt_ori.v.bak
.........\edcrypt_ori_p.srs
.........\edcrypt_ori_test.v
.........\edcrypt_ori_test.v.bak
.........\keyexp_ori_p.srs
.........\key_expand_ori.v
.........\key_expand_ori.v.bak
.........\reference_result.v
.........\reference_result.v.bak
.........\sbox.bak
.........\sbox.v
.........\sbox.v.bak
.........\sms4.mpf
.........\sms4_control_ori.v
.........\sms4_control_ori.v.bak
.........\sms4_control_ori_p.srs
.........\sms4_de_ori_test.v
.........\sms4_de_ori_test.v.bak
.........\sms4_de_reference.mpf
.........\sms4_de_reference.v
.........\sms4_de_reference.v.bak
.........\sms4_en_ori_test.v
.........\sms4_en_ori_test.v.bak
.........\sms4_ori.v
.........\sms4_ori.v.bak
.........\sms4_ori_test1.v
.........\sms4_ori_test1.v.bak
.........\sms4_ori_test_00.v
.........\sms4_ori_test_00.v.bak
.........\sms4_ori_test_01.v
.........\sms4_ori_test_01.v.bak
.........\sms4_reference.v
.........\sms4_reference.v.bak
.........\timescale.v
.........\timescale.v.bak
.........\transcript
.........\vish_stacktrace.vstf
.........\vsim.wlf
.........\vsim_stacktrace.vstf
.........\work
.........\....\@b@k_@s@h@i@f@t0
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@b@k_@s@h@i@f@t1
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@b@k_@s@h@i@f@t2
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@b_@s@h@i@f@t0
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\@b_@s@h@i@f@t1
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\@b_@s@h@i@f@t2
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\@b_@s@h@i@f@t3
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\@b_@s@h@i@f@t4
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\@c@k
.........\....\....\verilog.asm
.........\....\....\_primary.dat

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