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new_compare

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 352kb
  • Downloaded :0次
  • Author :杨***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
This is a timing comparator, when the data a and b when a high number of consistent data, we can design according to their own amendments to the relevant parameters
Packet file list
(Preview for download)
new_compare
...........\compare1.bsf
...........\compare1.done
...........\compare1.flow.rpt
...........\compare1.map.eqn
...........\compare1.map.rpt
...........\compare1.map.summary
...........\compare1.qarlog
...........\compare1.qpf
...........\compare1.qsf
...........\compare1.qws
...........\compare1.sim.rpt
...........\compare1.vhd
...........\compare1.vhd.bak
...........\counter.bsf
...........\counter.vhd
...........\counter.vhd.bak
...........\counter.vwf
...........\db
...........\..\compare1.cbx.xml
...........\..\compare1.cmp.rdb
...........\..\compare1.dbp
...........\..\compare1.db_info
...........\..\compare1.eco.cdb
...........\..\compare1.eds_overflow
...........\..\compare1.fnsim.cdb
...........\..\compare1.fnsim.hdb
...........\..\compare1.fnsim.qmsg
...........\..\compare1.hier_info
...........\..\compare1.hif
...........\..\compare1.map.bpm
...........\..\compare1.map.cdb
...........\..\compare1.map.ecobp
...........\..\compare1.map.hdb
...........\..\compare1.map.logdb
...........\..\compare1.map.qmsg
...........\..\compare1.map_bb.cdb
...........\..\compare1.map_bb.hdb
...........\..\compare1.map_bb.logdb
...........\..\compare1.pre_map.cdb
...........\..\compare1.pre_map.hdb
...........\..\compare1.psp
...........\..\compare1.pss
...........\..\compare1.qpf
...........\..\compare1.rtlv.hdb
...........\..\compare1.rtlv_sg.cdb
...........\..\compare1.rtlv_sg_swap.cdb
...........\..\compare1.sgdiff.cdb
...........\..\compare1.sgdiff.hdb
...........\..\compare1.sim.cvwf
...........\..\compare1.sim.hdb
...........\..\compare1.sim.qmsg
...........\..\compare1.sim.rdb
...........\..\compare1.sld_design_entry.sci
...........\..\compare1.sld_design_entry_dsc.sci
...........\..\compare1.syn_hier_info
...........\..\new_compare.cbx.xml
...........\..\new_compare.cmp.rdb
...........\..\new_compare.dbp
...........\..\new_compare.db_info
...........\..\new_compare.eco.cdb
...........\..\new_compare.eds_overflow
...........\..\new_compare.fnsim.cdb
...........\..\new_compare.fnsim.hdb
...........\..\new_compare.fnsim.qmsg
...........\..\new_compare.hier_info
...........\..\new_compare.hif
...........\..\new_compare.map.bpm
...........\..\new_compare.map.cdb
...........\..\new_compare.map.ecobp
...........\..\new_compare.map.hdb
...........\..\new_compare.map.logdb
...........\..\new_compare.map.qmsg
...........\..\new_compare.map_bb.cdb
...........\..\new_compare.map_bb.hdb
...........\..\new_compare.map_bb.logdb
...........\..\new_compare.pre_map.cdb
...........\..\new_compare.pre_map.hdb
...........\..\new_compare.psp
...........\..\new_compare.pss
...........\..\new_compare.rtlv.hdb
...........\..\new_compare.rtlv_sg.cdb
...........\..\new_compare.rtlv_sg_swap.cdb
...........\..\new_compare.sgdiff.cdb
...........\..\new_compare.sgdiff.hdb
...........\..\new_compare.sim.cvwf
...........\..\new_compare.sim.hdb
...........\..\new_compare.sim.qmsg
...........\..\new_compare.sim.rdb
...........\..\new_compare.sld_design_entry.sci
...........\..\new_compare.sld_design_entry_dsc.sci
...........\..\new_compare.syn_hier_info
...........\..\new_duty.cbx.xml
...........\..\new_duty.cmp.rdb
...........\..\new_duty.dbp
...........\..\new_duty.db_info
...........\..\new_duty.eco.cdb
...........\..\new_duty.eds_overflow
...........\..\new_duty.fnsim.hdb
...........\..\new_duty.fnsim.qmsg
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