The UART reference design band cache is used for Xinlix for fpga-uart reference design with cache for Xinlix for FPGA

A6850.csf
A6850.psf
A6850.quartus
A6850.ssf
A6850.VHD
A6850TB2.VHD
A6850TOP.VHD
Altera Reference Design License Agreement.TXT
BRKMUX.VHD
BUS_CNTL.VHD
CNTL_REG.VHD
DATACNT.VHD
DATAMUX.VHD
DATCOUNT.VHD
Debug.fsf
ds6850.pdf
FRAMERR.VHD
MUX.VHD
PARGEN.VHD
PAR_TREE.VHD
RCV_REG.VHD
Release.fsf
RXCNTL.VHD
RXCNTLSM.VHD
RXCOUNT.VHD
RXSHFTRG.VHD
RX_STSRG.VHD
SRPARGEN.VHD
STSRG.VHD
TCNTL.VHD
TRANSM.VHD
TSHFTRG.VHD
TXCLKCNT.VHD
TX_STSRG.VHD
XMIT_REG.VHD

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