Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 5kb
  • Downloaded :0次
  • Author :z****
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
Contains the main function of the electronic clock, input CLK for 1KHZ, output for the dynamic scan 8 CLD show. There are alarm, on-time time, time to adjust. Adjustment can display flashes. The clock for the 24-hour clock. Curriculum design excellence through. platform: MAX+ PLUS2.
Packet file list
(Preview for download)
zyj
...\cnt0.vhd
...\deco10.vhd
...\divclk.vhd
...\sysctrl0.vhd
...\testf0.gdf
...\timec.vhd
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.