Counter latch 12 registers with load, clr functions such as two-foot register (clocked bidirectional pin) a simple state machine synchronous state machine with a state machine design data interface controller traffic lights a simple UART test vectors (Test Bench), for example: source corresponding adder adder test bench test bench)

verilog实例
...........\12位寄存器.v
...........\transcript
...........\Verilog HDL 实例说明.doc
...........\一个同步状态机.txt
...........\一个简单的UART.v
...........\一个简单的状态机.v
...........\元件例化与层次设计.txt
...........\双向脚（clocked bidirectional pin）.txt
...........\带load，clr等功能的寄存器.v
...........\用状态机设计的交通灯控制器.v
...........\相应加法器的测试向量（test bench).v
...........\计数器.v
...........\锁存器.v

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