In the Quartus simulation procedures adopted by the transposition of the VHDL code

reg_add
.......\cmp_state.ini
.......\db
.......\..\add_sub_7vh.tdf
.......\..\add_sub_f0i.tdf
.......\..\add_sub_g0i.tdf
.......\..\add_sub_h0i.tdf
.......\..\add_sub_l2i.tdf
.......\..\add_sub_o0i.tdf
.......\..\reg_add.asm.qmsg
.......\..\reg_add.cbx.xml
.......\..\reg_add.cmp.cdb
.......\..\reg_add.cmp.hdb
.......\..\reg_add.cmp.logdb
.......\..\reg_add.cmp.rdb
.......\..\reg_add.cmp.tdb
.......\..\reg_add.cmp0.ddb
.......\..\reg_add.cmp2.ddb
.......\..\reg_add.db_info
.......\..\reg_add.eco.cdb
.......\..\reg_add.eds_overflow
.......\..\reg_add.fit.qmsg
.......\..\reg_add.fnsim.hdb
.......\..\reg_add.hier_info
.......\..\reg_add.hif
.......\..\reg_add.map.cdb
.......\..\reg_add.map.hdb
.......\..\reg_add.map.logdb
.......\..\reg_add.map.qmsg
.......\..\reg_add.pre_map.cdb
.......\..\reg_add.pre_map.hdb
.......\..\reg_add.psp
.......\..\reg_add.rtlv.hdb
.......\..\reg_add.rtlv_sg.cdb
.......\..\reg_add.rtlv_sg_swap.cdb
.......\..\reg_add.sgdiff.cdb
.......\..\reg_add.sgdiff.hdb
.......\..\reg_add.signalprobe.cdb
.......\..\reg_add.sim.hdb
.......\..\reg_add.sim.qmsg
.......\..\reg_add.sim.rdb
.......\..\reg_add.sim.vwf
.......\..\reg_add.sld_design_entry.sci
.......\..\reg_add.sld_design_entry_dsc.sci
.......\..\reg_add.syn_hier_info
.......\..\reg_add.tan.qmsg
.......\..\reg_add_cmp.qrpt
.......\..\reg_add_sim.qrpt
.......\reg_add.asm.rpt
.......\reg_add.bsf
.......\reg_add.done
.......\reg_add.fit.eqn
.......\reg_add.fit.rpt
.......\reg_add.fit.summary
.......\reg_add.flow.rpt
.......\reg_add.map.eqn
.......\reg_add.map.rpt
.......\reg_add.map.summary
.......\reg_add.pin
.......\reg_add.qpf
.......\reg_add.qsf
.......\reg_add.qws
.......\reg_add.sim.rpt
.......\reg_add.tan.rpt
.......\reg_add.tan.summary
.......\reg_add.vhd
.......\reg_add.vwf

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