err

vhdl
....\func_sim
....\........\brst_cntr.vhd
....\........\cslt_cntr.vhd
....\........\ki_cntr.vhd
....\........\load.do
....\........\mt48lc1m16a1.v
....\........\mti_pkg.vhd
....\........\rcd_cntr.vhd
....\........\ref_cntr.vhd
....\........\run_sim.do
....\........\sdrm.vhd
....\........\sdrmc_state.vhd
....\........\sdrm_t.vhd
....\........\state.do
....\........\sys_int.vhd
....\........\tb_sdrm.v
....\........\transcript
....\........\verwave.do
....\........\work
....\........\....\brst_cntr
....\........\....\.........\brst_cntr_arch.asm
....\........\....\.........\brst_cntr_arch.dat
....\........\....\.........\_primary.dat
....\........\....\cslt_cntr
....\........\....\.........\cslt_cntr_arch.asm
....\........\....\.........\cslt_cntr_arch.dat
....\........\....\.........\_primary.dat
....\........\....\ki_cntr
....\........\....\.......\ki_cntr_arch.asm
....\........\....\.......\ki_cntr_arch.dat
....\........\....\.......\_primary.dat
....\........\....\mt48lc1m16a1
....\........\....\............\verilog.asm
....\........\....\............\_primary.dat
....\........\....\............\_primary.vhd
....\........\....\mti_pkg
....\........\....\.......\body.asm
....\........\....\.......\body.dat
....\........\....\.......\_primary.dat
....\........\....\.......\_vhdl.asm
....\........\....\rcd_cntr
....\........\....\........\rcd_cntr_arch.asm
....\........\....\........\rcd_cntr_arch.dat
....\........\....\........\_primary.dat
....\........\....\ref_cntr
....\........\....\........\ref_cntr_arch.asm
....\........\....\........\ref_cntr_arch.dat
....\........\....\........\_primary.dat
....\........\....\sdrm
....\........\....\....\sdrm_arch.asm
....\........\....\....\sdrm_arch.dat
....\........\....\....\_primary.dat
....\........\....\sdrmc_state
....\........\....\...........\sdrmc_state_arch.asm
....\........\....\...........\sdrmc_state_arch.dat
....\........\....\...........\_primary.dat
....\........\....\sdrm_t
....\........\....\......\sdrm_t_arch.asm
....\........\....\......\sdrm_t_arch.dat
....\........\....\......\_primary.dat
....\........\....\sys_int
....\........\....\.......\sys_int_arch.asm
....\........\....\.......\sys_int_arch.dat
....\........\....\.......\_primary.dat
....\........\....\t_sdrm
....\........\....\......\testbench.asm
....\........\....\......\testbench.dat
....\........\....\......\verilog.asm
....\........\....\......\_primary.dat
....\........\....\......\_primary.vhd
....\........\....\_info
....\micron
....\......\bank0.txt
....\......\bank1.txt
....\......\mt48lc1m16a1-8a.v
....\......\mt48lc1m16a1.v
....\......\test.v
....\par
....\...\sdrm.bit
....\...\sdrm.edf
....\...\sdrm.ll
....\...\sdrm.ncf
....\...\xproj
....\...\.....\sdrm.xpj
....\...\.....\ver1
....\...\.....\....\netlist.lst
....\...\.....\....\rev1
....\...\.....\....\....\bitgen.ut
....\...\.....\....\....\command.his
....\...\.....\....\....\fe.log
....\...\.....\....\....\map.mrp
....\...\.....\....\....\map.ncd
....\...\.....\....\....\map.ngm
....\...\.....\....\....\ngd2ver.log
....\...\.....\....\....\ngd2vhdl.log
....\...\.....\....\....\program.his
....\...\.....\....\....\revision.obf
....\...\.....\....\....\revision.rbf
....\...\.....\....\....\rptbrwsr.dat

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