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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.32mb
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  • Author :周***
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Introduction - If you have any usage issues, please Google them yourself
The source of the introduction ADS7844 AD conversion of the VHDL controller chip.
Packet file list
(Preview for download)
ads7844
.......\addr_1.vhd
.......\ads7844.asm.rpt
.......\ads7844.bdf
.......\ads7844.done
.......\ads7844.dpf
.......\ads7844.fit.rpt
.......\ads7844.fit.smsg
.......\ads7844.fit.summary
.......\ads7844.flow.rpt
.......\ads7844.map.rpt
.......\ads7844.map.summary
.......\ads7844.mif_update.rpt
.......\ads7844.pin
.......\ads7844.pof
.......\ads7844.qpf
.......\ads7844.qsf
.......\ads7844.qws
.......\ads7844.sim.rpt
.......\ads7844.sof
.......\ads7844.tan.rpt
.......\ads7844.tan.summary
.......\ads7844.vwf
.......\ads7844_assignment_defaults.qdf
.......\altshift_taps0.bsf
.......\altshift_taps0.cmp
.......\altshift_taps0.vhd
.......\altshift_taps1.bsf
.......\altshift_taps1.cmp
.......\altshift_taps1.vhd
.......\altsyncram0.bsf
.......\altsyncram0.cmp
.......\altsyncram0.vhd





.......\altsyncram0_waveforms.html
.......\cs_pulse.bdf
.......\cs_wide.vhd
.......\db
.......\..\ads7844.asm.qmsg
.......\..\ads7844.cbx.xml
.......\..\ads7844.cmp.cdb
.......\..\ads7844.cmp.hdb
.......\..\ads7844.cmp.logdb
.......\..\ads7844.cmp.rdb
.......\..\ads7844.cmp.tdb
.......\..\ads7844.cmp0.ddb
.......\..\ads7844.dbp
.......\..\ads7844.db_info
.......\..\ads7844.eco.cdb
.......\..\ads7844.fit.qmsg
.......\..\ads7844.hier_info
.......\..\ads7844.hif
.......\..\ads7844.map.cdb
.......\..\ads7844.map.hdb
.......\..\ads7844.map.logdb
.......\..\ads7844.map.qmsg
.......\..\ads7844.pre_map.cdb
.......\..\ads7844.pre_map.hdb
.......\..\ads7844.psp
.......\..\ads7844.pss
.......\..\ads7844.rpp.qmsg
.......\..\ads7844.rtlv.hdb
.......\..\ads7844.rtlv_sg.cdb
.......\..\ads7844.rtlv_sg_swap.cdb
.......\..\ads7844.sgate.rvd
.......\..\ads7844.sgate_sm.rvd
.......\..\ads7844.sgdiff.cdb
.......\..\ads7844.sgdiff.hdb
.......\..\ads7844.signalprobe.cdb
.......\..\ads7844.sim.vwf
.......\..\ads7844.sld_design_entry.sci
.......\..\ads7844.sld_design_entry_dsc.sci
.......\..\ads7844.smp_dump.txt
.......\..\ads7844.syn_hier_info
.......\..\ads7844.tan.qmsg
.......\..\altsyncram_jjl1.tdf
.......\..\altsyncram_s7m1.tdf
.......\..\prev_cmp_ads7844.asm.qmsg
.......\..\prev_cmp_ads7844.fit.qmsg
.......\..\prev_cmp_ads7844.map.qmsg
.......\..\prev_cmp_ads7844.tan.qmsg
.......\..\wed.zsf
.......\dff_2.vhd
.......\d_latch.bdf
.......\fq.vhd
.......\fq_cs.vhd
.......\from_ad.bdf
.......\lpm_shiftreg0.bsf
.......\lpm_shiftreg0.cmp
.......\lpm_shiftreg0.vhd
.......\lpm_shiftreg1.bsf
.......\lpm_shiftreg1.cmp
.......\lpm_shiftreg1.vhd
.......\lpm_shiftreg2.bsf
.......\lpm_shiftreg2.cmp
.......\lpm_shiftreg2.vhd
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