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firfilter

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.57mb
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Introduction - If you have any usage issues, please Google them yourself
The realization of a FIR filter, type-type algorithm based on direct input data width: 8-bit output data width: 16 bands: 16 bands converted by the filter (shifted to right 16-bit) for the characteristic parameters: h [0] = h [15] = 0000h [1] = h [14] = 0065h [2] = h [13] = 018F h [3] = h [12] = 035A h [4] = h [11] = 0579h [5] = h [10] = 078E h [6] = h [9] = 0935h [7] = h [8] = 0A1F
Packet file list
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firfilter
.........\220model.v
.........\db
.........\..\add_sub_4dh.tdf
.........\..\add_sub_6dh.tdf
.........\..\add_sub_7dh.tdf
.........\..\add_sub_8dh.tdf
.........\..\add_sub_adh.tdf
.........\..\add_sub_bdh.tdf
.........\..\firfilter.asm.qmsg
.........\..\firfilter.asm_labs.ddb
.........\..\firfilter.cbx.xml
.........\..\firfilter.cmp.bpm
.........\..\firfilter.cmp.cdb
.........\..\firfilter.cmp.ecobp
.........\..\firfilter.cmp.hdb
.........\..\firfilter.cmp.logdb
.........\..\firfilter.cmp.rdb
.........\..\firfilter.cmp.tdb
.........\..\firfilter.cmp0.ddb
.........\..\firfilter.cmp_bb.cdb
.........\..\firfilter.cmp_bb.hdb
.........\..\firfilter.cmp_bb.logdb
.........\..\firfilter.cmp_bb.rcf
.........\..\firfilter.dbp
.........\..\firfilter.db_info
.........\..\firfilter.eco.cdb
.........\..\firfilter.eds_overflow
.........\..\firfilter.fit.qmsg
.........\..\firfilter.hier_info
.........\..\firfilter.hif
.........\..\firfilter.map.bpm
.........\..\firfilter.map.cdb
.........\..\firfilter.map.ecobp
.........\..\firfilter.map.hdb
.........\..\firfilter.map.logdb
.........\..\firfilter.map.qmsg
.........\..\firfilter.map_bb.cdb
.........\..\firfilter.map_bb.hdb
.........\..\firfilter.map_bb.logdb
.........\..\firfilter.pre_map.cdb
.........\..\firfilter.pre_map.hdb
.........\..\firfilter.psp
.........\..\firfilter.pss
.........\..\firfilter.rtlv.hdb
.........\..\firfilter.rtlv_sg.cdb
.........\..\firfilter.rtlv_sg_swap.cdb
.........\..\firfilter.sgdiff.cdb
.........\..\firfilter.sgdiff.hdb
.........\..\firfilter.signalprobe.cdb
.........\..\firfilter.sim.cvwf
.........\..\firfilter.sim.hdb
.........\..\firfilter.sim.qmsg
.........\..\firfilter.sim.rdb
.........\..\firfilter.sld_design_entry.sci
.........\..\firfilter.sld_design_entry_dsc.sci
.........\..\firfilter.sta.qmsg
.........\..\firfilter.sta.rdb
.........\..\firfilter.syn_hier_info
.........\..\firfilter.tan.qmsg
.........\..\mult_r7q.tdf
.........\..\prev_cmp_firfilter.asm.qmsg
.........\..\prev_cmp_firfilter.fit.qmsg
.........\..\prev_cmp_firfilter.map.qmsg
.........\..\prev_cmp_firfilter.sim.qmsg
.........\..\prev_cmp_firfilter.sta.qmsg
.........\..\prev_cmp_firfilter.tan.qmsg
.........\..\wed.wsf
.........\firfilter.asm.rpt
.........\firfilter.done
.........\firfilter.fit.rpt
.........\firfilter.fit.smsg
.........\firfilter.fit.summary
.........\firfilter.flow.rpt
.........\firfilter.map.smsg
.........\firfilter.map.summary
.........\firfilter.pin
.........\firfilter.pof
.........\firfilter.qpf
.........\firfilter.qsf
.........\firfilter.qws
.........\firfilter.sdc
.........\firfilter.sim.rpt
.........\firfilter.sof
.........\firfilter.sta.rpt
.........\firfilter.sta.summary
.........\firfilter.tan.rpt
.........\firfilter.tan.summary
.........\firfilter.v
.........\firfilter.v.bak
.........\firfilter.vwf
.........\fir_in.salt
.........\fir_out.txt
.........\mult.v
.........\prev_cmp_firfilter.qmsg
.........\tb_firfilter.v
.........\tb_firfilter.v.bak
.........\vish_stacktrace.vstf
.........\vsim.wlf
.........\work
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