4 digital LED dynamic display of the Verilog HDL source code, it can dynamically display 4-digit for the FPGA to facilitate the DEBUG, very classic, easy-to-read, and after Modelsim/ISE/FPGA (XC3S250ETQ144) authentication and realize, good The behavior model should be shared.

dynamic display
...............\dynamic display.v
...............\dynamic display.v.bak
...............\ise
...............\...\device_usage_statistics.html
...............\...\dynamic display.v
...............\...\ise.ise
...............\...\ise.ise_ISE_Backup
...............\...\ise.ntrc_log
...............\...\led_7seg.bgn
...............\...\led_7seg.bit
...............\...\LED_7seg.bld
...............\...\LED_7seg.cmd_log
...............\...\led_7seg.drc
...............\...\LED_7seg.lfp
...............\...\LED_7seg.lso
...............\...\LED_7seg.ncd
...............\...\LED_7seg.ngc
...............\...\LED_7seg.ngd
...............\...\LED_7seg.ngr
...............\...\LED_7seg.pad
...............\...\LED_7seg.par
...............\...\LED_7seg.pcf
...............\...\LED_7seg.prj
...............\...\LED_7seg.stx
...............\...\LED_7seg.syr
...............\...\led_7seg.twr
...............\...\led_7seg.twx
...............\...\LED_7seg.ucf
...............\...\LED_7seg.unroutes
...............\...\LED_7seg.ut
...............\...\LED_7seg.xpi
...............\...\LED_7seg.xst
...............\...\LED_7seg_map.mrp
...............\...\LED_7seg_map.ncd
...............\...\LED_7seg_map.ngm
...............\...\LED_7seg_pad.csv
...............\...\LED_7seg_pad.txt
...............\...\LED_7seg_prev_built.ngd
...............\...\LED_7seg_summary.html
...............\...\LED_7seg_usage.xml
...............\...\LED_7seg_vhdl.prj
...............\...\xst
...............\...\...\dump.xst
...............\...\...\........\LED_7seg.prj
...............\...\...\........\............\ngx
...............\...\...\........\............\...\notopt
...............\...\...\........\............\...\opt
...............\...\...\........\............\ntrc.scr
...............\...\...\projnav.tmp
...............\...\...\work
...............\...\...\....\hdllib.ref
...............\...\...\....\vlg42
...............\...\...\....\.....\_l_e_d__7seg.bin
...............\...\_impact.cmd
...............\...\_impact.log
...............\...\_ngo
...............\...\....\netlist.lst
...............\...\_pace.ucf
...............\...\_xmsgs
...............\...\......\bitgen.xmsgs
...............\...\......\map.xmsgs
...............\...\......\ngdbuild.xmsgs
...............\...\......\par.xmsgs
...............\...\......\trce.xmsgs
...............\...\......\xst.xmsgs
...............\test_dynamic_display.v
...............\test_dynamic_display.v.bak

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