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ac97_verilog_sourcecode

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 122kb
  • Downloaded :1次
  • Author :小***
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Introduction - If you have any usage issues, please Google them yourself
AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Packet file list
(Preview for download)
ac97_ctrl
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Entries.Log
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\...\Template
.........\.....\verilog
.........\.....\.......\ac97_codec_sin.v
.........\.....\.......\ac97_codec_sout.v
.........\.....\.......\ac97_codec_top.v
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\...\Template
.........\.....\.......\tests.v
.........\.....\.......\test_bench_top.v
.........\.....\.......\wb_mast_model.v
.........\.....\.......\wb_model_defines.v
.........\CVS
.........\...\Entries
.........\...\Entries.Log
.........\...\Repository
.........\...\Root
.........\...\Template
.........\doc
.........\...\ac97_doc.pdf
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
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.........\...\README.txt
.........\...\STATUS.txt
.........\rtl
.........\...\CVS
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.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\verilog
.........\...\.......\ac97_cra.v
.........\...\.......\ac97_defines.v
.........\...\.......\ac97_dma_if.v
.........\...\.......\ac97_dma_req.v
.........\...\.......\ac97_fifo_ctrl.v
.........\...\.......\ac97_int.v
.........\...\.......\ac97_in_fifo.v
.........\...\.......\ac97_out_fifo.v
.........\...\.......\ac97_prc.v
.........\...\.......\ac97_rf.v
.........\...\.......\ac97_rst.v
.........\...\.......\ac97_sin.v
.........\...\.......\ac97_soc.v
.........\...\.......\ac97_sout.v
.........\...\.......\ac97_top.v
.........\...\.......\ac97_wb_if.v
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
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.........\sim
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.........\...\rtl_sim
.........\...\.......\bin
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.........\...\.......\...\...\Repository
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.........\...\.......\...\...\Template
.........\...\.......\...\Makefile
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.........\...\.......\...\Template
.........\...\.......\run
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.........\...\.......\...\Makefile
.........\syn
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.........\...\...\comp.dc
.........\...\...\CVS
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