Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.

fpu
...\add_sub27_arch.vhd
...\div_r2_arch.vhd
...\except_arch.vhd
...\fpu_arch.vhd
...\fpu_compile_scr.txt
...\mul_r2_arch.vhd
...\post_norm_arch.vhd
...\pre_norm_arch.vhd
...\pre_norm_fmul_arch.vhd

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