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digital_clock

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.13mb
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  • Author :屠****
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Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed annotation. Suitable for learning Verilog
Packet file list
(Preview for download)
digital_clock
.............\device_usage_statistics.html
.............\de_bounce.v
.............\de_bounce_summary.html
.............\digital_clock.ise
.............\digital_clock.ise_ISE_Backup
.............\digital_clock.ntrc_log
.............\digital_clock.v
.............\digital_clock_summary.html
.............\hc164_driver.v
.............\hc164_driver_summary.html
.............\top_digital_clock.bgn
.............\top_digital_clock.bit
.............\top_digital_clock.bld
.............\top_digital_clock.cel
.............\top_digital_clock.cmd_log
.............\top_digital_clock.drc
.............\top_digital_clock.lso
.............\top_digital_clock.ncd
.............\top_digital_clock.ngc
.............\top_digital_clock.ngd
.............\top_digital_clock.ngr
.............\top_digital_clock.pad
.............\top_digital_clock.par
.............\top_digital_clock.pcf
.............\top_digital_clock.prj
.............\top_digital_clock.stx
.............\top_digital_clock.syr
.............\top_digital_clock.twr
.............\top_digital_clock.twx
.............\top_digital_clock.ucf
.............\top_digital_clock.unroutes
.............\top_digital_clock.ut
.............\top_digital_clock.v
.............\top_digital_clock.xpi
.............\top_digital_clock.xst
.............\top_digital_clock_last_par.ncd
.............\top_digital_clock_map.mrp
.............\top_digital_clock_map.ncd
.............\top_digital_clock_map.ngm
.............\top_digital_clock_pad.csv
.............\top_digital_clock_pad.txt
.............\top_digital_clock_prev_built.ngd
.............\top_digital_clock_summary.html
.............\top_digital_clock_usage.xml
.............\top_digital_clock_vhdl.prj
.............\xst
.............\...\dump.xst
.............\...\........\top_digital_clock.prj
.............\...\........\.....................\ngx
.............\...\........\.....................\...\notopt
.............\...\........\.....................\...\opt
.............\...\........\.....................\ntrc.scr
.............\...\projnav.tmp
.............\...\work
.............\...\....\hdllib.ref
.............\...\....\vlg15
.............\...\....\.....\hc164__driver.bin
.............\...\....\vlg4F
.............\...\....\.....\top__digital__clock.bin
.............\...\....\vlg78
.............\...\....\.....\de__bounce.bin
.............\...\....\vlg7D
.............\...\....\.....\digital__clock.bin
.............\_impact.cmd
.............\_impact.log
.............\_ngo
.............\....\netlist.lst
.............\_xmsgs
.............\......\bitgen.xmsgs
.............\......\map.xmsgs
.............\......\ngdbuild.xmsgs
.............\......\par.xmsgs
.............\......\trce.xmsgs
.............\......\xst.xmsgs
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