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newsdram

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.99mb
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8 Reading SDRAM verilog to write 8 procedures
Packet file list
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newsdram
........\db
........\..\add_sub_1sh.tdf
........\..\add_sub_5sh.tdf
........\..\add_sub_fth.tdf
........\..\add_sub_gth.tdf
........\..\add_sub_rod.tdf
........\..\altsyncram_4d31.tdf
........\..\cntr_2gc.tdf
........\..\mem_ctrl1.analyze_file.qmsg
........\..\mem_ctrl1.cbx.xml
........\..\mem_ctrl1.cmp.kpt
........\..\mem_ctrl1.cmp.rdb
........\..\mem_ctrl1.dbp
........\..\mem_ctrl1.db_info
........\..\mem_ctrl1.eco.cdb
........\..\mem_ctrl1.eds_overflow
........\..\mem_ctrl1.fit.qmsg
........\..\mem_ctrl1.fnsim.hdb
........\..\mem_ctrl1.fnsim.qmsg
........\..\mem_ctrl1.hier_info
........\..\mem_ctrl1.hif
........\..\mem_ctrl1.map.cdb
........\..\mem_ctrl1.map.hdb
........\..\mem_ctrl1.map.logdb
........\..\mem_ctrl1.map.qmsg
........\..\mem_ctrl1.pre_map.cdb
........\..\mem_ctrl1.pre_map.hdb
........\..\mem_ctrl1.psp
........\..\mem_ctrl1.rtlv.hdb
........\..\mem_ctrl1.rtlv_sg.cdb
........\..\mem_ctrl1.rtlv_sg_swap.cdb
........\..\mem_ctrl1.sgdiff.cdb
........\..\mem_ctrl1.sgdiff.hdb
........\..\mem_ctrl1.sim.hdb
........\..\mem_ctrl1.sim.qmsg
........\..\mem_ctrl1.sim.rdb
........\..\mem_ctrl1.sim.vwf
........\..\mem_ctrl1.sld_design_entry.sci
........\..\mem_ctrl1.sld_design_entry_dsc.sci
........\..\mem_ctrl1.smp_dump.txt
........\..\mem_ctrl1.syn_hier_info
........\..\sd_if.cbx.xml
........\..\sd_if.cmp.kpt
........\..\sd_if.cmp.rdb
........\..\sd_if.dbp
........\..\sd_if.db_info
........\..\sd_if.eco.cdb
........\..\sd_if.fit.qmsg
........\..\sd_if.hier_info
........\..\sd_if.hif
........\..\sd_if.map.cdb
........\..\sd_if.map.hdb
........\..\sd_if.map.logdb
........\..\sd_if.map.qmsg
........\..\sd_if.pre_map.cdb
........\..\sd_if.pre_map.hdb
........\..\sd_if.psp
........\..\sd_if.rtlv.hdb
........\..\sd_if.rtlv_sg.cdb
........\..\sd_if.rtlv_sg_swap.cdb
........\..\sd_if.sgdiff.cdb
........\..\sd_if.sgdiff.hdb
........\..\sd_if.sld_design_entry.sci
........\..\sd_if.sld_design_entry_dsc.sci
........\..\sd_if.smp_dump.txt
........\..\sd_if.syn_hier_info
........\..\sd_top.asm.qmsg
........\..\sd_top.cbx.xml
........\..\sd_top.cmp.cdb
........\..\sd_top.cmp.hdb
........\..\sd_top.cmp.logdb
........\..\sd_top.cmp.rdb
........\..\sd_top.cmp.tdb
........\..\sd_top.cmp0.ddb
........\..\sd_top.dbp
........\..\sd_top.db_info
........\..\sd_top.eco.cdb
........\..\sd_top.eds_overflow
........\..\sd_top.fit.qmsg
........\..\sd_top.hier_info
........\..\sd_top.hif
........\..\sd_top.map.cdb
........\..\sd_top.map.hdb
........\..\sd_top.map.logdb
........\..\sd_top.map.qmsg
........\..\sd_top.pre_map.cdb
........\..\sd_top.pre_map.hdb
........\..\sd_top.psp
........\..\sd_top.rtlv.hdb
........\..\sd_top.rtlv_sg.cdb
........\..\sd_top.rtlv_sg_swap.cdb
........\..\sd_top.sgdiff.cdb
........\..\sd_top.sgdiff.hdb
........\..\sd_top.sim.hdb
........\..\sd_top.sim.qmsg
........\..\sd_top.sim.rdb
........\..\sd_top.sim.vwf
........\..\sd_top.sld_design_entry.sci
........\..\sd_top.sld_design_entry_dsc.sci
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