URAT asynchronous communication interface VHDL description can be integrated

UART_VHDL
.........\db
.........\..\UART_top.asm.qmsg
.........\..\UART_top.asm_labs.ddb
.........\..\UART_top.cbx.xml
.........\..\UART_top.cmp.cdb
.........\..\UART_top.cmp.hdb
.........\..\UART_top.cmp.kpt
.........\..\UART_top.cmp.logdb
.........\..\UART_top.cmp.rdb
.........\..\UART_top.cmp.tdb
.........\..\UART_top.cmp0.ddb
.........\..\UART_top.dbp
.........\..\UART_top.db_info
.........\..\UART_top.eco.cdb
.........\..\UART_top.fit.qmsg
.........\..\UART_top.hier_info
.........\..\UART_top.hif
.........\..\UART_top.map.cdb
.........\..\UART_top.map.hdb
.........\..\UART_top.map.logdb
.........\..\UART_top.map.qmsg
.........\..\UART_top.pre_map.cdb
.........\..\UART_top.pre_map.hdb
.........\..\UART_top.psp
.........\..\UART_top.rtlv.hdb
.........\..\UART_top.rtlv_sg.cdb
.........\..\UART_top.rtlv_sg_swap.cdb
.........\..\UART_top.sgdiff.cdb
.........\..\UART_top.sgdiff.hdb
.........\..\UART_top.signalprobe.cdb
.........\..\UART_top.sld_design_entry.sci
.........\..\UART_top.sld_design_entry_dsc.sci
.........\..\UART_top.smp_dump.txt
.........\..\UART_top.syn_hier_info
.........\..\UART_top.tan.qmsg
.........\intface.vhd
.........\modem.vhd
.........\rxcver.vhd
.........\txmitt.vhd
.........\uart_5kvg_top.vhd
.........\uart_int_tb.vhd
.........\uart_rxerr_tb.vhd
.........\uart_rx_tb.vhd
.........\UART_top.asm.rpt
.........\UART_top.done
.........\UART_top.fit.rpt
.........\UART_top.fit.smsg
.........\UART_top.fit.summary
.........\UART_top.flow.rpt
.........\UART_top.map.rpt
.........\UART_top.map.summary
.........\UART_top.pin
.........\UART_top.pof
.........\UART_top.qpf
.........\UART_top.qsf
.........\UART_top.qws
.........\UART_top.sof
.........\UART_top.tan.rpt
.........\UART_top.tan.summary
.........\uart_top.vhd
.........\uart_tx_tb.vhd

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