Using Verilog HDL realize the 1553B avionics bus interface.

1553b_v
.......\1553_enc_dec
.......\............\1553_enc_dec.asm.rpt
.......\............\1553_enc_dec.bdf
.......\............\1553_enc_dec.done
.......\............\1553_enc_dec.fit.eqn
.......\............\1553_enc_dec.fit.rpt
.......\............\1553_enc_dec.fit.summary
.......\............\1553_enc_dec.flow.rpt
.......\............\1553_enc_dec.map.eqn
.......\............\1553_enc_dec.map.rpt
.......\............\1553_enc_dec.map.summary
.......\............\1553_enc_dec.qpf
.......\............\1553_enc_dec.qsf
.......\............\1553_enc_dec.qws
.......\............\1553_enc_dec.sim.rpt
.......\............\1553_enc_dec.tan.rpt
.......\............\1553_enc_dec.tan.summary
.......\............\1553_enc_dec.vwf
.......\............\cmp_state.ini
.......\............\db
.......\............\..\1553_enc_dec.asm.qmsg
.......\............\..\1553_enc_dec.cmp.cdb
.......\............\..\1553_enc_dec.cmp.ddb
.......\............\..\1553_enc_dec.cmp.hdb
.......\............\..\1553_enc_dec.cmp.rdb
.......\............\..\1553_enc_dec.cmp.tdb
.......\............\..\1553_enc_dec.dat_manager.dat
.......\............\..\1553_enc_dec.db_info
.......\............\..\1553_enc_dec.fit.qmsg
.......\............\..\1553_enc_dec.hier_info
.......\............\..\1553_enc_dec.hif
.......\............\..\1553_enc_dec.map.cdb
.......\............\..\1553_enc_dec.map.hdb
.......\............\..\1553_enc_dec.map.qmsg
.......\............\..\1553_enc_dec.pre_map.hdb
.......\............\..\1553_enc_dec.project.hdb
.......\............\..\1553_enc_dec.rtlv.hdb
.......\............\..\1553_enc_dec.rtlv_sg.cdb
.......\............\..\1553_enc_dec.rtlv_sg_swap.cdb
.......\............\..\1553_enc_dec.sgdiff.cdb
.......\............\..\1553_enc_dec.sgdiff.hdb
.......\............\..\1553_enc_dec.sim.hdb
.......\............\..\1553_enc_dec.sim.qmsg
.......\............\..\1553_enc_dec.sim.rdb
.......\............\..\1553_enc_dec.sim.vwf
.......\............\..\1553_enc_dec.sld_design_entry.sci
.......\............\..\1553_enc_dec.sld_design_entry_dsc.sci
.......\............\..\1553_enc_dec.syn_hier_info
.......\............\..\1553_enc_dec.tan.qmsg
.......\............\..\1553_enc_dec_cmp.qrpt
.......\............\..\1553_enc_dec_sim.qrpt
.......\............\..\cntr_e18.tdf
.......\............\..\cntr_m08.tdf
.......\............\decoder_1553.v
.......\............\docs
.......\............\....\rd1021.pdf
.......\............\....\readme.txt
.......\............\encoder_1553.v
.......\............\par
.......\............\...\EC
.......\............\...\..\decoder_1553.prf
.......\............\...\..\decoder_1553.syn
.......\............\...\..\encoder_1553.prf
.......\............\...\..\encoder_1553.syn
.......\............\serv_req_info.txt
.......\............\sim.cfg
.......\............\simulation
.......\............\..........\EC
.......\............\..........\..\scripts
.......\............\..........\..\.......\runsim_1553.do
.......\............\source
.......\............\......\decoder_1553.v
.......\............\......\encoder_1553.v
.......\............\synthesis
.......\............\.........\EC
.......\............\.........\..\synplify
.......\............\.........\..\........\decoder_1553.prj
.......\............\.........\..\........\decoder_1553.sdc
.......\............\.........\..\........\encoder_1553.prj
.......\............\.........\..\........\encoder_1553.sdc
.......\............\testbench
.......\............\.........\test_1553.v
.......\............\tests
.......\............\.....\readme.txt
.......\............\undo_redo.txt

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