This is the sequence detector. Have a serial sequence is defined as the clock and the corresponding control signal, producing a stable single-bit output signal monitor means the corresponding clock input sequence level, monitoring the sequence of the existence of the default sequence, whether from the first few enter a start, as long as there is, always monitored. Monitoring to be marked.

x
.\db
.\..\half_clk.asm.qmsg
.\..\half_clk.cbx.xml
.\..\half_clk.cmp.cdb
.\..\half_clk.cmp.hdb
.\..\half_clk.cmp.kpt
.\..\half_clk.cmp.logdb
.\..\half_clk.cmp.qrpt
.\..\half_clk.cmp.rdb
.\..\half_clk.cmp.tdb
.\..\half_clk.cmp0.ddb
.\..\half_clk.dbp
.\..\half_clk.db_info
.\..\half_clk.eco.cdb
.\..\half_clk.eds_overflow
.\..\half_clk.epe.qmsg
.\..\half_clk.fit.qmsg
.\..\half_clk.fnsim.hdb
.\..\half_clk.fnsim.qmsg
.\..\half_clk.hier_info
.\..\half_clk.hif
.\..\half_clk.map.cdb
.\..\half_clk.map.hdb
.\..\half_clk.map.logdb
.\..\half_clk.map.qmsg
.\..\half_clk.pre_map.cdb
.\..\half_clk.pre_map.hdb
.\..\half_clk.psp
.\..\half_clk.rpp.qmsg
.\..\half_clk.rtlv.hdb
.\..\half_clk.rtlv_sg.cdb
.\..\half_clk.rtlv_sg_swap.cdb
.\..\half_clk.sgate.rvd
.\..\half_clk.sgate_sm.rvd
.\..\half_clk.sgdiff.cdb
.\..\half_clk.sgdiff.hdb
.\..\half_clk.sim.hdb
.\..\half_clk.sim.qmsg
.\..\half_clk.sim.rdb
.\..\half_clk.sim.vwf
.\..\half_clk.sld_design_entry.sci
.\..\half_clk.sld_design_entry_dsc.sci
.\..\half_clk.syn_hier_info
.\..\half_clk.tan.qmsg
.\..\wed.zsf
.\half_clk.asm.rpt
.\half_clk.cdf
.\half_clk.done
.\half_clk.dpf
.\half_clk.epe.rpt
.\half_clk.epe.summary
.\half_clk.fit.rpt
.\half_clk.fit.smsg
.\half_clk.fit.summary
.\half_clk.flow.rpt
.\half_clk.hex
.\half_clk.hexout
.\half_clk.jbc
.\half_clk.map.rpt
.\half_clk.map.summary
.\half_clk.pin
.\half_clk.pof
.\half_clk.qpf
.\half_clk.qsf
.\half_clk.qws
.\half_clk.sim.rpt
.\half_clk.sof
.\half_clk.tan.rpt
.\half_clk.tan.summary
.\half_clk.v
.\half_clk.vwf
.\output_file.pof

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