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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 305kb
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Introduction - If you have any usage issues, please Google them yourself
Used to realize the occurrence VGA timing, display color, with CPLD realize
Packet file list
(Preview for download)
altpll0.bsf
altpll0.ppf
altpll0.v
altpll0_bb.v
altpll0_inst.v

altpll0_waveforms.html
Block1.bdf
chip_editor.acv
cmp_state.ini
lpm_fifo_dc0.bsf
lpm_fifo_dc0.v
lpm_fifo_dc0_bb.v


lpm_fifo_dc0_waveforms.html
quartus_nativelink_synthesis.log
sim.cfg
timescale.v
VGA.asm.rpt
VGA.bdf
VGA.bsf
VGA.done
VGA.dpf
VGA.drc.rpt
VGA.eda.rpt
VGA.fit.eqn
VGA.fit.rpt
VGA.fit.smsg
VGA.fit.summary
VGA.fld
VGA.flow.rpt
VGA.map.eqn
VGA.map.rpt
VGA.map.smsg
VGA.map.summary
VGA.pin
VGA.pof
VGA.qpf
VGA.qsf
VGA.qws
VGA.sim.rpt
VGA.sof
VGA.tan.rpt
VGA.tan.summary
VGA.vwf
vga_addr.v
VGA_assignment_defaults.qdf
vga_tgen.v
vga_tgen.v.bak
vga_vtim.v
vga_vtim.v.bak
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