This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help

Random Number generator library
...............................\bench
...............................\.....\vhdl
...............................\.....\....\math_lib.vhd
...............................\.....\....\rng_lib.vhd
...............................\.....\....\tb_rng.vhd
...............................\doc
...............................\...\copying.txt
...............................\...\src
...............................\...\...\random_ug.doc
...............................\readme.txt

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