The EDA is a very good programming, is the Electronic Design Competition during the preparation I was proud to one capable of producing sine, cosine, square wave (variable duty cycle), triangle wave, sawtooth wave and a variety of superimposed waveforms, can be设置.

DDS_all
.......\AD9850.h
.......\ADDER10B.bsf
.......\ADDER10B.VHD
.......\ADDER32B.bsf
.......\ADDER32B.VHD
.......\cmp_state.ini
.......\DATA
.......\....\LUT10X10.HEX
.......\....\LUT10X10.MIF
.......\db
.......\..\altsyncram_5m82.tdf
.......\..\altsyncram_63p.tdf
.......\..\altsyncram_8kc2.tdf
.......\..\altsyncram_gmu.tdf
.......\..\altsyncram_kol2.tdf
.......\..\altsyncram_lo82.tdf
.......\..\altsyncram_sq71.tdf
.......\..\cntr_0r9.tdf
.......\..\cntr_1u6.tdf
.......\..\cntr_2u6.tdf
.......\..\cntr_619.tdf
.......\..\cntr_8b8.tdf
.......\..\cntr_dn7.tdf
.......\..\cntr_e29.tdf
.......\..\cntr_en8.tdf
.......\..\cntr_hv7.tdf
.......\..\cntr_kv8.tdf
.......\..\cntr_mk7.tdf
.......\..\cntr_mo8.tdf
.......\..\cntr_nt9.tdf
.......\..\cntr_pd8.tdf
.......\..\DDS_ALL.asm.qmsg
.......\..\DDS_ALL.cbx.xml
.......\..\DDS_ALL.cmp.cdb
.......\..\DDS_ALL.cmp.hdb
.......\..\DDS_ALL.cmp.kpt
.......\..\DDS_ALL.cmp.logdb
.......\..\DDS_ALL.cmp.rdb
.......\..\DDS_ALL.cmp.tdb
.......\..\DDS_ALL.cmp0.ddb
.......\..\DDS_ALL.dbp
.......\..\DDS_ALL.db_info
.......\..\DDS_ALL.eco.cdb
.......\..\DDS_ALL.fit.qmsg
.......\..\DDS_ALL.hier_info
.......\..\DDS_ALL.hif
.......\..\DDS_ALL.map.cdb
.......\..\DDS_ALL.map.hdb
.......\..\DDS_ALL.map.logdb
.......\..\DDS_ALL.map.qmsg
.......\..\DDS_ALL.pre_map.cdb
.......\..\DDS_ALL.pre_map.hdb
.......\..\DDS_ALL.psp
.......\..\DDS_ALL.rtlv.hdb
.......\..\DDS_ALL.rtlv_sg.cdb
.......\..\DDS_ALL.rtlv_sg_swap.cdb
.......\..\DDS_ALL.sgdiff.cdb
.......\..\DDS_ALL.sgdiff.hdb
.......\..\DDS_ALL.signalprobe.cdb
.......\..\DDS_ALL.sld_design_entry.sci
.......\..\DDS_ALL.sld_design_entry_dsc.sci
.......\..\DDS_ALL.syn_hier_info
.......\..\DDS_ALL.tan.qmsg
.......\..\DDS_ALL_cmp.qrpt
.......\..\dds_vhdl.asm.qmsg
.......\..\dds_vhdl.cmp.cdb
.......\..\dds_vhdl.cmp.ddb
.......\..\dds_vhdl.cmp.hdb
.......\..\dds_vhdl.cmp.rdb
.......\..\dds_vhdl.cmp.tdb
.......\..\dds_vhdl.dat_manager.dat
.......\..\dds_vhdl.db_info
.......\..\dds_vhdl.fit.qmsg
.......\..\dds_vhdl.hier_info
.......\..\dds_vhdl.hif
.......\..\dds_vhdl.icc
.......\..\dds_vhdl.map.cdb
.......\..\dds_vhdl.map.hdb
.......\..\dds_vhdl.map.qmsg
.......\..\dds_vhdl.pre_map.hdb
.......\..\dds_vhdl.project.hdb
.......\..\dds_vhdl.rpp.qmsg
.......\..\dds_vhdl.rtlv.hdb
.......\..\dds_vhdl.rtlv_sg.cdb
.......\..\dds_vhdl.rtlv_sg_swap.cdb
.......\..\dds_vhdl.sgate.rvd
.......\..\dds_vhdl.sgdiff.cdb
.......\..\dds_vhdl.sgdiff.hdb
.......\..\dds_vhdl.signalprobe.cdb
.......\..\dds_vhdl.sim.hdb
.......\..\dds_vhdl.sim.qmsg
.......\..\dds_vhdl.sim.rdb
.......\..\dds_vhdl.sld_design_entry.sci
.......\..\dds_vhdl.sld_design_entry_dsc.sci
.......\..\dds_vhdl.syn_hier_info
.......\..\dds_vhdl.tan.qmsg
.......\..\dds_vhdl_cmp.qrpt
.......\..\dds_vhdl_sim.qrpt
.......\..\decode_9ie.tdf

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