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pg_070731

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 6.3mb
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Introduction - If you have any usage issues, please Google them yourself
FPGA-based screen test procedure, based on testing requirements in the host computer under the control of a variety of graphics generated images, and adjust the parameters
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pg_070731
.........\ahdl i2c core
.........\.............\expander.tdf
.........\.............\i2cslave.inc
.........\.............\i2cslave.tdf
.........\blcoksize.inc
.........\blocksize.tdf
.........\buffer_ram.bsf
.........\buffer_ram.cmp
.........\buffer_ram.inc
.........\buffer_ram.vhd
.........\buf_ram.bsf
.........\buf_ram.cmp
.........\buf_ram.inc
.........\buf_ram.vhd
.........\certaingrayscales.inc
.........\certaingrayscales.tdf
.........\cmp_state.ini
.........\cyclic.asm.rpt
.........\cyclic.cdf
.........\cyclic.csf
.........\cyclic.done
.........\cyclic.drc.rpt
.........\cyclic.fit.eqn
.........\cyclic.fit.rpt
.........\cyclic.fit.summary
.........\cyclic.fld
.........\cyclic.flow.rpt
.........\cyclic.jam
.........\cyclic.map.eqn
.........\cyclic.map.rpt
.........\cyclic.map.summary
.........\cyclic.merge.rpt
.........\cyclic.pin
.........\cyclic.pof
.........\cyclic.qpf
.........\cyclic.qsf
.........\cyclic.qws
.........\cyclic.rbf
.........\cyclic.SLD_HUB_INST.map.eqn
.........\cyclic.sof
.........\cyclic.tan.rpt
.........\cyclic.tan.summary
.........\cyclic.ttf
.........\cyclic.vhd
.........\cyclic_assignment_defaults.qdf
.........\data_blue.cmp
.........\data_blue.vhd
.........\data_green.cmp
.........\data_green.vhd
.........\data_red.cmp
.........\data_red.vhd
.........\db
.........\..\add_sub_48b.tdf
.........\..\add_sub_4g8.tdf
.........\..\add_sub_5c8.tdf
.........\..\add_sub_5g8.tdf
.........\..\add_sub_6g8.tdf
.........\..\add_sub_ave.tdf
.........\..\add_sub_c2g.tdf
.........\..\add_sub_j6b.tdf
.........\..\add_sub_jvg.tdf
.........\..\add_sub_k4h.tdf
.........\..\add_sub_ke8.tdf
.........\..\add_sub_le8.tdf
.........\..\add_sub_me8.tdf
.........\..\add_sub_mtf.tdf
.........\..\add_sub_ne8.tdf
.........\..\add_sub_ntf.tdf
.........\..\add_sub_nuf.tdf
.........\..\add_sub_oe8.tdf
.........\..\add_sub_pe8.tdf
.........\..\add_sub_q4h.tdf
.........\..\add_sub_qe8.tdf
.........\..\add_sub_qpg.tdf
.........\..\add_sub_r0h.tdf
.........\..\add_sub_ra8.tdf
.........\..\add_sub_re8.tdf
.........\..\add_sub_se8.tdf
.........\..\add_sub_spg.tdf
.........\..\add_sub_t0h.tdf
.........\..\altsyncram_07n.tdf
.........\..\altsyncram_0ih1.tdf
.........\..\altsyncram_0jm.tdf
.........\..\altsyncram_0lm.tdf
.........\..\altsyncram_0un.tdf
.........\..\altsyncram_1tn.tdf
.........\..\altsyncram_2ia2.tdf
.........\..\altsyncram_2jm.tdf
.........\..\altsyncram_2lm.tdf
.........\..\altsyncram_3fq1.tdf
.........\..\altsyncram_3lm.tdf
.........\..\altsyncram_3un.tdf
.........\..\altsyncram_46h1.tdf
.........\..\altsyncram_46n.tdf
.........\..\altsyncram_4fq1.tdf
.........\..\altsyncram_4tn.tdf
.........\..\altsyncram_5fq1.tdf
.........\..\altsyncram_66h1.tdf
.........\..\altsyncram_67n.tdf
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