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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 202kb
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  • Author :fish*****
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Introduction - If you have any usage issues, please Google them yourself
4 Enter a binary number, use the dial code switches that make light-emitting diodes show the four binary number.
Packet file list
(Preview for download)
seg7_1a
.......\cmp_state.ini
.......\db
.......\..\seg7_1.asm.qmsg
.......\..\seg7_1.cmp.cdb
.......\..\seg7_1.cmp.ddb
.......\..\seg7_1.cmp.hdb
.......\..\seg7_1.cmp.rdb
.......\..\seg7_1.cmp.tdb
.......\..\seg7_1.db_info
.......\..\seg7_1.fit.qmsg
.......\..\seg7_1.hier_info
.......\..\seg7_1.hif
.......\..\seg7_1.map.cdb
.......\..\seg7_1.map.hdb
.......\..\seg7_1.map.qmsg
.......\..\seg7_1.pre_map.hdb
.......\..\seg7_1.project.hdb
.......\..\seg7_1.rtlv.hdb
.......\..\seg7_1.rtlv_sg.cdb
.......\..\seg7_1.rtlv_sg_swap.cdb
.......\..\seg7_1.sgdiff.cdb
.......\..\seg7_1.sgdiff.hdb
.......\..\seg7_1.sld_design_entry.sci
.......\..\seg7_1.sld_design_entry_dsc.sci
.......\..\seg7_1.syn_hier_info
.......\..\seg7_1.tan.qmsg
.......\..\seg7_1a.asm.qmsg
.......\..\seg7_1a.cmp.cdb
.......\..\seg7_1a.cmp.ddb
.......\..\seg7_1a.cmp.hdb
.......\..\seg7_1a.cmp.rdb
.......\..\seg7_1a.cmp.tdb
.......\..\seg7_1a.db_info
.......\..\seg7_1a.fit.qmsg
.......\..\seg7_1a.hier_info
.......\..\seg7_1a.hif
.......\..\seg7_1a.map.cdb
.......\..\seg7_1a.map.hdb
.......\..\seg7_1a.map.qmsg
.......\..\seg7_1a.pre_map.hdb
.......\..\seg7_1a.project.hdb
.......\..\seg7_1a.rtlv.hdb
.......\..\seg7_1a.rtlv_sg.cdb
.......\..\seg7_1a.rtlv_sg_swap.cdb
.......\..\seg7_1a.sgdiff.cdb
.......\..\seg7_1a.sgdiff.hdb
.......\..\seg7_1a.sim.hdb
.......\..\seg7_1a.sim.qmsg
.......\..\seg7_1a.sim.rdb
.......\..\seg7_1a.sld_design_entry.sci
.......\..\seg7_1a.sld_design_entry_dsc.sci
.......\..\seg7_1a.syn_hier_info
.......\..\seg7_1a.tan.qmsg
.......\..\seg7_1a_cmp.qrpt
.......\..\seg7_1a_sim.qrpt
.......\..\seg7_1_cmp.qrpt
.......\seg7_1.asm.rpt
.......\seg7_1.done
.......\seg7_1.fit.eqn
.......\seg7_1.fit.rpt
.......\seg7_1.fit.summary
.......\seg7_1.flow.rpt
.......\seg7_1.map.eqn
.......\seg7_1.map.rpt
.......\seg7_1.map.summary
.......\seg7_1.pin
.......\seg7_1.pof
.......\seg7_1.qpf
.......\seg7_1.qsf
.......\seg7_1.qws
.......\seg7_1.tan.rpt
.......\seg7_1.tan.summary
.......\seg7_1.vhd
.......\seg7_1a.asm.rpt
.......\seg7_1a.done
.......\seg7_1a.fit.eqn
.......\seg7_1a.fit.rpt
.......\seg7_1a.fit.summary
.......\seg7_1a.flow.rpt
.......\seg7_1a.map.eqn
.......\seg7_1a.map.rpt
.......\seg7_1a.map.summary
.......\seg7_1a.pin
.......\seg7_1a.pof
.......\seg7_1a.qpf
.......\seg7_1a.qsf
.......\seg7_1a.qws
.......\seg7_1a.sim.rpt
.......\seg7_1a.tan.rpt
.......\seg7_1a.tan.summary
.......\seg7_1a.vhd
.......\seg7_1a.vwf
.......\sim.cfg
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