The use of Verilog language, the design of crossovers, it is a good reference

fenpin
......\counter10.bsf
......\counter11.bsf
......\counter11.v
......\couter10.v
......\db
......\..\fen_pin_10_1.asm.qmsg
......\..\fen_pin_10_1.asm_labs.ddb
......\..\fen_pin_10_1.cbx.xml
......\..\fen_pin_10_1.cmp.cdb
......\..\fen_pin_10_1.cmp.hdb
......\..\fen_pin_10_1.cmp.kpt
......\..\fen_pin_10_1.cmp.logdb
......\..\fen_pin_10_1.cmp.rdb
......\..\fen_pin_10_1.cmp.tdb
......\..\fen_pin_10_1.cmp0.ddb
......\..\fen_pin_10_1.cmp2.ddb
......\..\fen_pin_10_1.dbp
......\..\fen_pin_10_1.db_info
......\..\fen_pin_10_1.eco.cdb
......\..\fen_pin_10_1.eda.qmsg
......\..\fen_pin_10_1.eds_overflow
......\..\fen_pin_10_1.fit.qmsg
......\..\fen_pin_10_1.fnsim.cdb
......\..\fen_pin_10_1.fnsim.hdb
......\..\fen_pin_10_1.fnsim.qmsg
......\..\fen_pin_10_1.hier_info
......\..\fen_pin_10_1.hif
......\..\fen_pin_10_1.map.cdb
......\..\fen_pin_10_1.map.hdb
......\..\fen_pin_10_1.map.logdb
......\..\fen_pin_10_1.map.qmsg
......\..\fen_pin_10_1.pre_map.cdb
......\..\fen_pin_10_1.pre_map.hdb
......\..\fen_pin_10_1.psp
......\..\fen_pin_10_1.rtlv.hdb
......\..\fen_pin_10_1.rtlv_sg.cdb
......\..\fen_pin_10_1.rtlv_sg_swap.cdb
......\..\fen_pin_10_1.sgdiff.cdb
......\..\fen_pin_10_1.sgdiff.hdb
......\..\fen_pin_10_1.signalprobe.cdb
......\..\fen_pin_10_1.sim.hdb
......\..\fen_pin_10_1.sim.qmsg
......\..\fen_pin_10_1.sim.rdb
......\..\fen_pin_10_1.sim.vwf
......\..\fen_pin_10_1.sld_design_entry.sci
......\..\fen_pin_10_1.sld_design_entry_dsc.sci
......\..\fen_pin_10_1.syn_hier_info
......\..\fen_pin_10_1.tan.qmsg
......\..\wed.zsf
......\enable.bsf
......\enable.v
......\fen_pin_10_1.asm.rpt
......\fen_pin_10_1.bdf
......\fen_pin_10_1.done
......\fen_pin_10_1.eda.rpt
......\fen_pin_10_1.fit.rpt
......\fen_pin_10_1.fit.smsg
......\fen_pin_10_1.fit.summary
......\fen_pin_10_1.flow.rpt
......\fen_pin_10_1.map.rpt
......\fen_pin_10_1.map.summary
......\fen_pin_10_1.pin
......\fen_pin_10_1.pof
......\fen_pin_10_1.qpf
......\fen_pin_10_1.qsf
......\fen_pin_10_1.qws
......\fen_pin_10_1.sim.rpt
......\fen_pin_10_1.sof
......\fen_pin_10_1.tan.rpt
......\fen_pin_10_1.tan.summary
......\simulation
......\..........\fen_pin_10_1.vwf
......\..........\modelsim
......\..........\........\fen_pin_10_1.vo
......\..........\........\fen_pin_10_1_modelsim.xrf
......\..........\........\fen_pin_10_1_v.sdo

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