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DDR2_module_VHDL_test(Rev0.1)

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 123kb
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  • Author :骑***
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Introduction - If you have any usage issues, please Google them yourself
ddr 2 interface test module ddr 2 read and write interface to read and write test module
Packet file list
(Preview for download)
DDR2_64Mx8_HY5PS12821BFP_ModelSim
.................................\hynix
.................................\.....\e
.................................\.....\.\a.asm
.................................\.....\.\a.dat
.................................\.....\.\_primary.dat
.................................\.....\hy5ps12821bf
.................................\.....\............\bev.asm
.................................\.....\............\bev.dat
.................................\.....\............\_primary.dat
.................................\.....\hy5ps12821bf_pack
.................................\.....\.................\body.asm
.................................\.....\.................\body.dat
.................................\.....\.................\_primary.dat
.................................\.....\.................\_vhdl.asm
.................................\.....\_info
.................................\README
.................................\run
.................................\run_com
.................................\run_sim
.................................\run_vec
.................................\TB_HY5PS12821BF.vhd
.................................\test_vec.c
.................................\test_vec.dat
.................................\test_vec_512mddr2_x8.h
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