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clock_design

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 405kb
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  • Author :屈***
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Digital Clock in Verilog code, quartusII development environment.
Packet file list
(Preview for download)
clock_design
............\bianma.bsf
............\bianma.v
............\db
............\..\add_sub_1sh.tdf
............\..\shuzibiao.asm.qmsg
............\..\shuzibiao.cbx.xml
............\..\shuzibiao.cmp.cdb
............\..\shuzibiao.cmp.hdb
............\..\shuzibiao.cmp.kpt
............\..\shuzibiao.cmp.logdb
............\..\shuzibiao.cmp.rdb
............\..\shuzibiao.cmp.tdb
............\..\shuzibiao.cmp0.ddb
............\..\shuzibiao.dbp
............\..\shuzibiao.db_info
............\..\shuzibiao.eco.cdb
............\..\shuzibiao.eds_overflow
............\..\shuzibiao.fit.qmsg
............\..\shuzibiao.fnsim.cdb
............\..\shuzibiao.fnsim.hdb
............\..\shuzibiao.fnsim.qmsg
............\..\shuzibiao.hier_info
............\..\shuzibiao.hif
............\..\shuzibiao.map.cdb
............\..\shuzibiao.map.hdb
............\..\shuzibiao.map.logdb
............\..\shuzibiao.map.qmsg
............\..\shuzibiao.pre_map.cdb
............\..\shuzibiao.pre_map.hdb
............\..\shuzibiao.psp
............\..\shuzibiao.rtlv.hdb
............\..\shuzibiao.rtlv_sg.cdb
............\..\shuzibiao.rtlv_sg_swap.cdb
............\..\shuzibiao.sgdiff.cdb
............\..\shuzibiao.sgdiff.hdb
............\..\shuzibiao.signalprobe.cdb
............\..\shuzibiao.sim.hdb
............\..\shuzibiao.sim.qmsg
............\..\shuzibiao.sim.rdb
............\..\shuzibiao.sim.vwf
............\..\shuzibiao.sld_design_entry.sci
............\..\shuzibiao.sld_design_entry_dsc.sci
............\..\shuzibiao.smp_dump.txt
............\..\shuzibiao.syn_hier_info
............\..\shuzibiao.tan.qmsg
............\..\wed.zsf
............\LED.bsf
............\LED.v
............\main.bsf
............\main.v
............\shuzibiao.asm.rpt
............\shuzibiao.bdf
............\shuzibiao.done
............\shuzibiao.fit.rpt
............\shuzibiao.fit.smsg
............\shuzibiao.fit.summary
............\shuzibiao.flow.rpt
............\shuzibiao.map.rpt
............\shuzibiao.map.summary
............\shuzibiao.pin
............\shuzibiao.pof
............\shuzibiao.qpf
............\shuzibiao.qsf
............\shuzibiao.qws
............\shuzibiao.sim.rpt
............\shuzibiao.sof
............\shuzibiao.tan.rpt
............\shuzibiao.tan.summary
............\shuzibiao.vwf
............\sopc_builder_debug_log.txt
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