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ENCODE_SYSTEM

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 337kb
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  • Author :lipe*****
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Introduction - If you have any usage issues, please Google them yourself
Coding system, encoding of information, a complete description of VHDL source code
Packet file list
(Preview for download)
ENCODE_SYSTEM
.............\ata_ctrl.vhd
.............\ata_mux.vhd
.............\ata_pio_access.vhd
.............\comm_top.vhd
.............\control422.vhd
.............\controlall.vhd
.............\data_src.vhd
.............\dpram_rx.asy
.............\dpram_rx.edn
.............\dpram_rx.sym
.............\dpram_rx.v
.............\dpram_rx.veo
.............\dpram_rx.vhd
.............\dpram_rx.vho
.............\dpram_rx.xco
.............\dpram_rx_flist.txt
.............\dsp_peri.vhd
.............\ENCODE_SYSTEM.ise
.............\ENCODE_SYSTEM.ise_ISE_Backup
.............\fifo2sd.asy
.............\fifo2sd.edn
.............\fifo2sd.sym
.............\fifo2sd.v
.............\fifo2sd.veo
.............\fifo2sd.vhd
.............\fifo2sd.vho
.............\fifo2sd.xco
.............\fifo2sd_fifo_generator_v3_2_xst_1.ngc
.............\fifo2sd_flist.txt
.............\fsm_sdram.vhd
.............\interface_422.vhd
.............\ping_pong_buffer.vhd
.............\receiver.vhd
.............\receive_state.vhd
.............\receive_top.vhd
.............\sd2fifo.asy
.............\sd2fifo.edn
.............\sd2fifo.sym
.............\sd2fifo.v
.............\sd2fifo.veo
.............\sd2fifo.vhd
.............\sd2fifo.vho
.............\sd2fifo.xco
.............\sd2fifo_fifo_generator_v3_2_xst_1.ngc
.............\sd2fifo_flist.txt
.............\syscon.vhd
.............\system_reg.vhd
.............\system_top.ucf
.............\system_top.vhd
.............\system_top_summary.html
.............\system_tri_io.vhd
.............\templates
.............\.........\coregen.xml
.............\transmitter.vhd
.............\transmit_state.vhd
.............\transmit_top.vhd
.............\_xmsgs
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