A clock used to write VHDL code, the upload is project-type increase in the experimental plate is passed, for your reference

clock
.....\chip_editor.acv
.....\clock.asm.rpt
.....\clock.cdf
.....\clock.done
.....\clock.dpf
.....\clock.fit.eqn
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.eqn
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sof
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vhd
.....\clock_assignment_defaults.qdf
.....\cmp_state.ini
.....\count10.vhd
.....\count12.vhd
.....\count24.vhd
.....\count6.vhd
.....\db
.....\..\add_sub_soh.tdf
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.qrpt
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.fit.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\..\clock_cmp.qrpt
.....\..\clock_hier_info
.....\..\clock_syn_hier_info
.....\decoder7s.vhd
.....\division.vhd
.....\reg.vhd
.....\scan.vhd
.....\serv_req_info.txt
.....\timing.vhd
.....\timingrun.vhd

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