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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 199kb
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  • Author :徐***
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Introduction - If you have any usage issues, please Google them yourself
Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating
Packet file list
(Preview for download)
alu3
....\alu3.asm.rpt
....\alu3.done
....\alu3.fit.rpt
....\alu3.fit.summary
....\alu3.flow.rpt
....\alu3.map.rpt
....\alu3.map.smsg
....\alu3.map.summary
....\alu3.pin
....\alu3.pof
....\alu3.qpf
....\alu3.qsf
....\alu3.qws
....\alu3.sim.rpt
....\alu3.sof
....\alu3.tan.rpt
....\alu3.tan.summary
....\alu3.v
....\alu3.vwf
....\db
....\..\add_sub_8lh.tdf
....\..\add_sub_gnh.tdf
....\..\add_sub_rjh.tdf
....\..\add_sub_sjh.tdf
....\..\alu3.asm.qmsg
....\..\alu3.cbx.xml
....\..\alu3.cmp.cdb
....\..\alu3.cmp.hdb
....\..\alu3.cmp.logdb
....\..\alu3.cmp.rdb
....\..\alu3.cmp.tdb
....\..\alu3.cmp0.ddb
....\..\alu3.dbp
....\..\alu3.db_info
....\..\alu3.eco.cdb
....\..\alu3.eds_overflow
....\..\alu3.fit.qmsg
....\..\alu3.fnsim.cdb
....\..\alu3.fnsim.hdb
....\..\alu3.fnsim.qmsg
....\..\alu3.hier_info
....\..\alu3.hif
....\..\alu3.map.cdb
....\..\alu3.map.hdb
....\..\alu3.map.logdb
....\..\alu3.map.qmsg
....\..\alu3.pre_map.cdb
....\..\alu3.pre_map.hdb
....\..\alu3.psp
....\..\alu3.rtlv.hdb
....\..\alu3.rtlv_sg.cdb
....\..\alu3.rtlv_sg_swap.cdb
....\..\alu3.sgdiff.cdb
....\..\alu3.sgdiff.hdb
....\..\alu3.sim.hdb
....\..\alu3.sim.qmsg
....\..\alu3.sim.rdb
....\..\alu3.sim.vwf
....\..\alu3.sld_design_entry.sci
....\..\alu3.sld_design_entry_dsc.sci
....\..\alu3.syn_hier_info
....\..\alu3.tan.qmsg
....\..\wed.zsf
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