Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules

weifenqi
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........\..\wed.zsf
........\..\weifenqi.asm.qmsg
........\..\weifenqi.cbx.xml
........\..\weifenqi.cmp.cdb
........\..\weifenqi.cmp.hdb
........\..\weifenqi.cmp.kpt
........\..\weifenqi.cmp.logdb
........\..\weifenqi.cmp.rdb
........\..\weifenqi.cmp.tdb
........\..\weifenqi.cmp0.ddb
........\..\weifenqi.dbp
........\..\weifenqi.db_info
........\..\weifenqi.eco.cdb
........\..\weifenqi.eds_overflow
........\..\weifenqi.fit.qmsg
........\..\weifenqi.fnsim.cdb
........\..\weifenqi.fnsim.hdb
........\..\weifenqi.fnsim.qmsg
........\..\weifenqi.hier_info
........\..\weifenqi.hif
........\..\weifenqi.map.cdb
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........\..\weifenqi.map.logdb
........\..\weifenqi.map.qmsg
........\..\weifenqi.pre_map.cdb
........\..\weifenqi.pre_map.hdb
........\..\weifenqi.psp
........\..\weifenqi.rtlv.hdb
........\..\weifenqi.rtlv_sg.cdb
........\..\weifenqi.rtlv_sg_swap.cdb
........\..\weifenqi.sgdiff.cdb
........\..\weifenqi.sgdiff.hdb
........\..\weifenqi.signalprobe.cdb
........\..\weifenqi.sim.hdb
........\..\weifenqi.sim.qmsg
........\..\weifenqi.sim.rdb
........\..\weifenqi.sim_ori.vwf
........\..\weifenqi.sld_design_entry.sci
........\..\weifenqi.sld_design_entry_dsc.sci
........\..\weifenqi.syn_hier_info
........\..\weifenqi.tan.qmsg
........\weifenqi.asm.rpt
........\weifenqi.bdf
........\weifenqi.done
........\weifenqi.fit.rpt
........\weifenqi.fit.smsg
........\weifenqi.fit.summary
........\weifenqi.flow.rpt
........\weifenqi.map.rpt
........\weifenqi.map.summary
........\weifenqi.pin
........\weifenqi.pof
........\weifenqi.qpf
........\weifenqi.qsf
........\weifenqi.qws
........\weifenqi.sim.rpt
........\weifenqi.sof
........\weifenqi.tan.rpt
........\weifenqi.tan.summary
........\weifenqi.vwf
........\yicunqi.bdf
........\yicunqi.bsf
........\yicunqi.vwf

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