This is a simple to use VHDL to write the CPU process, a total of 10 commands support. Way to use microinstruction. Including. Bit file. Downloaded to the FPGA chip success. Do not forget to save notes carefully.

sum
...\.untf
...\automake.log
...\bitgen.ut
...\clock.bgn
...\clock.bit
...\clock.bld
...\clock.cmd_log
...\clock.drc
...\clock.lso
...\clock.mrp
...\clock.nc1
...\clock.ncd
...\clock.ngc
...\clock.ngd
...\clock.ngm
...\clock.ngr
...\clock.pad
...\clock.pad_txt
...\clock.par
...\clock.pcf
...\clock.placed_ncd_tracker
...\clock.prj
...\clock.routed_ncd_tracker
...\clock.stx
...\clock.syr
...\clock.twr
...\clock.twx
...\clock.ut
...\clock.vhdl
...\clock.xpi
...\clock_map.ncd
...\clock_map.ngm
...\clock_pad.csv
...\clock_pad.txt
...\coregen.log
...\coregen.prj
...\cu.vhd
...\fin.ANT
...\fin.fdo
...\fin.tbw
...\fin.udo
...\fin.vhw
...\ieu.cmd_log
...\ieu.lso
...\ieu.ngc
...\ieu.ngr
...\ieu.prj
...\ieu.stx
...\ieu.syr
...\ieu.vhdl
...\msi.vhdl
...\pepExtractor.prj
...\pp.ANT
...\pp.fdo
...\pp.tbw
...\pp.udo
...\pp.vhw
...\results.txt
...\ss.ANT
...\ss.fdo
...\ss.tbw
...\ss.udo
...\ss.vhw
...\sum.bgn
...\sum.bit
...\sum.bld
...\sum.cmd_log
...\sum.dhp
...\sum.drc
...\sum.lso
...\sum.mrp
...\sum.nc1
...\sum.ncd
...\sum.ngc
...\sum.ngd
...\sum.ngm
...\sum.ngr
...\sum.npl
...\sum.pad
...\sum.pad_txt
...\sum.par
...\sum.pcf
...\sum.placed_ncd_tracker
...\sum.prj
...\sum.routed_ncd_tracker
...\sum.stx
...\sum.syr
...\sum.twr
...\sum.twx
...\sum.ucf
...\sum.ucf.untf
...\sum.ut
...\sum.vhdl
...\sum.xpi
...\sum_last_par.ncd
...\sum_map.ncd
...\sum_map.ngm
...\sum_pad.csv
...\sum_pad.txt

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