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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.19mb
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  • Author :fspig*****
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Introduction - If you have any usage issues, please Google them yourself
I have written one of the 2008 competition in Beijing e-VHDL source
Packet file list
(Preview for download)
maxmin
......\ADC0820.bsf
......\ADC0820.vhd
......\calculate.bsf
......\calculate.vhd
......\change.vhd
......\db
......\..\add_sub_f4h.tdf
......\..\add_sub_ke8.tdf
......\..\add_sub_le8.tdf
......\..\add_sub_ma8.tdf
......\..\add_sub_me8.tdf
......\..\add_sub_ne8.tdf
......\..\add_sub_oe8.tdf
......\..\add_sub_pe8.tdf
......\..\add_sub_qa8.tdf
......\..\add_sub_qe8.tdf
......\..\add_sub_re8.tdf
......\..\add_sub_se8.tdf
......\..\alt_u_div_hld.tdf
......\..\alt_u_div_jod.tdf
......\..\decode_9ie.tdf
......\..\lpm_divide_5nf.tdf
......\..\lpm_divide_klf.tdf
......\..\maxmin.asm.qmsg
......\..\maxmin.cbx.xml
......\..\maxmin.cmp.cdb
......\..\maxmin.cmp.hdb
......\..\maxmin.cmp.qrpt
......\..\maxmin.cmp.rdb
......\..\maxmin.cmp.tdb
......\..\maxmin.cmp0.ddb
......\..\maxmin.dbp
......\..\maxmin.db_info
......\..\maxmin.eco.cdb
......\..\maxmin.fit.qmsg
......\..\maxmin.hier_info
......\..\maxmin.hif
......\..\maxmin.map.cdb
......\..\maxmin.map.hdb
......\..\maxmin.map.qmsg
......\..\maxmin.pre_map.cdb
......\..\maxmin.pre_map.hdb
......\..\maxmin.psp
......\..\maxmin.rpp.qmsg
......\..\maxmin.rtlv.hdb
......\..\maxmin.rtlv_sg.cdb
......\..\maxmin.rtlv_sg_swap.cdb
......\..\maxmin.sgate.rvd
......\..\maxmin.sgate_sm.rvd
......\..\maxmin.sgdiff.cdb
......\..\maxmin.sgdiff.hdb
......\..\maxmin.signalprobe.cdb
......\..\maxmin.sld_design_entry.sci
......\..\maxmin.sld_design_entry_dsc.sci
......\..\maxmin.smp_dump.txt
......\..\maxmin.syn_hier_info
......\..\maxmin.tan.qmsg
......\..\sign_div_unsign_7jg.tdf
......\..\sign_div_unsign_mhg.tdf
......\display1.bsf
......\display1.vhd
......\maxmin
......\......\ADC0820.bsf
......\......\ADC0820.vhd
......\......\calculate.bsf
......\......\calculate.vhd
......\......\change.vhd
......\......\db
......\......\..\add_sub_f4h.tdf
......\......\..\add_sub_ke8.tdf
......\......\..\add_sub_le8.tdf
......\......\..\add_sub_ma8.tdf
......\......\..\add_sub_me8.tdf
......\......\..\add_sub_ne8.tdf
......\......\..\add_sub_oe8.tdf
......\......\..\add_sub_pe8.tdf
......\......\..\add_sub_qa8.tdf
......\......\..\add_sub_qe8.tdf
......\......\..\add_sub_re8.tdf
......\......\..\add_sub_se8.tdf
......\......\..\alt_u_div_hld.tdf
......\......\..\alt_u_div_jod.tdf
......\......\..\decode_9ie.tdf
......\......\..\lpm_divide_5nf.tdf
......\......\..\lpm_divide_klf.tdf
......\......\..\maxmin.db_info
......\......\..\maxmin.eco.cdb
......\......\..\maxmin.sld_design_entry.sci
......\......\..\sign_div_unsign_7jg.tdf
......\......\..\sign_div_unsign_mhg.tdf
......\......\display1.bsf
......\......\display1.vhd
......\......\maxmin.asm.rpt
......\......\maxmin.bdf
......\......\maxmin.cdf
......\......\maxmin.done
......\......\maxmin.dpf
......\......\maxmin.fit.eqn
......\......\maxmin.fit.rpt
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