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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 227kb
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  • Author :余****
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Introduction - If you have any usage issues, please Google them yourself
Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Packet file list
(Preview for download)
clock
.....\Block1.bdf
.....\db
.....\..\REL_clock.analyze_file.qmsg
.....\..\REL_clock.asm.qmsg
.....\..\REL_clock.cbx.xml
.....\..\REL_clock.cmp.cdb
.....\..\REL_clock.cmp.hdb
.....\..\REL_clock.cmp.kpt
.....\..\REL_clock.cmp.logdb
.....\..\REL_clock.cmp.rdb
.....\..\REL_clock.cmp.tdb
.....\..\REL_clock.cmp0.ddb
.....\..\REL_clock.dbp
.....\..\REL_clock.db_info
.....\..\REL_clock.eco.cdb
.....\..\REL_clock.eds_overflow
.....\..\REL_clock.fit.qmsg
.....\..\REL_clock.hier_info
.....\..\REL_clock.hif
.....\..\REL_clock.map.cdb
.....\..\REL_clock.map.hdb
.....\..\REL_clock.map.logdb
.....\..\REL_clock.map.qmsg
.....\..\REL_clock.pre_map.cdb
.....\..\REL_clock.pre_map.hdb
.....\..\REL_clock.psp
.....\..\REL_clock.rtlv.hdb
.....\..\REL_clock.rtlv_sg.cdb
.....\..\REL_clock.rtlv_sg_swap.cdb
.....\..\REL_clock.sgdiff.cdb
.....\..\REL_clock.sgdiff.hdb
.....\..\REL_clock.signalprobe.cdb
.....\..\REL_clock.sim.hdb
.....\..\REL_clock.sim.qmsg
.....\..\REL_clock.sim.rdb
.....\..\REL_clock.sim.vwf
.....\..\REL_clock.sld_design_entry.sci
.....\..\REL_clock.sld_design_entry_dsc.sci
.....\..\REL_clock.syn_hier_info
.....\..\REL_clock.tan.qmsg
.....\..\wed.zsf
.....\REL_clock.asm.rpt
.....\REL_clock.done
.....\REL_clock.fit.rpt
.....\REL_clock.fit.smsg
.....\REL_clock.fit.summary
.....\REL_clock.flow.rpt
.....\REL_clock.map.rpt
.....\REL_clock.map.summary
.....\REL_clock.pin
.....\REL_clock.pof
.....\REL_clock.qpf
.....\REL_clock.qsf
.....\REL_clock.qws
.....\REL_clock.sim.rpt
.....\REL_clock.sof
.....\REL_clock.tan.rpt
.....\REL_clock.tan.summary
.....\REL_clock.vhd
.....\REL_clock.vwf
.....\REL_clock_description.txt
.....\shuzizhong.bsf
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