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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 628kb
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This procedure for XILINX SPARTEN-3E development board LED lights control, can realize the control rules have lights flashing.
Packet file list
(Preview for download)
LED
...\data
...\....\myip.ucf
...\etc
...\...\download.cmd
...\...\fast_runtime.opt
...\myip.bsb
...\myip.log
...\myip.mhs
...\myip.mss
...\myip.xmp
...\MyProcessorIPLib
...\................\drivers
...\................\.......\ip_v1_00_a
...\................\.......\..........\data
...\................\.......\..........\....\ip_v2_1_0.mdd
...\................\.......\..........\....\ip_v2_1_0.tcl
...\................\.......\..........\src
...\................\.......\..........\...\ip.c
...\................\.......\..........\...\ip.h
...\................\.......\..........\...\ip_selftest.c
...\................\.......\..........\...\Makefile
...\................\pcores
...\................\......\ip_v1_00_a
...\................\......\..........\data
...\................\......\..........\....\ip_v2_1_0.mpd
...\................\......\..........\....\ip_v2_1_0.pao
...\................\......\..........\devl
...\................\......\..........\....\ipwiz.log
...\................\......\..........\....\ipwiz.opt
...\................\......\..........\....\projnav
...\................\......\..........\....\.......\automake.log
...\................\......\..........\....\.......\ip.cli
...\................\......\..........\....\.......\ip.ise
...\................\......\..........\....\.......\ip.ise_ISE_Backup
...\................\......\..........\....\.......\_xmsgs
...\................\......\..........\....\.......\__projnav.log
...\................\......\..........\....\README.txt
...\................\......\..........\....\synthesis
...\................\......\..........\....\.........\ip_xst.prj
...\................\......\..........\....\.........\ip_xst.scr
...\................\......\..........\hdl
...\................\......\..........\...\vhdl
...\................\......\..........\...\....\ip.vhd
...\................\......\..........\...\....\transcript
...\................\......\..........\...\....\user_logic.vhd
...\pcores
...\......\MyProcessorIPLib
...\......\................\drivers
...\......\................\.......\ip_v1_00_a
...\......\................\.......\..........\data
...\......\................\.......\..........\....\ip_v2_1_0.mdd
...\......\................\.......\..........\....\ip_v2_1_0.tcl
...\......\................\.......\..........\src
...\......\................\.......\..........\...\ip.c
...\......\................\.......\..........\...\ip.h
...\......\................\.......\..........\...\ip_selftest.c
...\......\................\.......\..........\...\Makefile
...\......\................\pcores
...\......\................\......\ip_v1_00_a
...\......\................\......\..........\data
...\......\................\......\..........\....\ip_v2_1_0.mpd
...\......\................\......\..........\....\ip_v2_1_0.pao
...\......\................\......\..........\devl
...\......\................\......\..........\....\ipwiz.log
...\......\................\......\..........\....\ipwiz.opt
...\......\................\......\..........\....\projnav
...\......\................\......\..........\....\.......\automake.log
...\......\................\......\..........\....\.......\ip.cli
...\......\................\......\..........\....\.......\ip.ise
...\......\................\......\..........\....\.......\ip.ise_ISE_Backup
...\......\................\......\..........\....\.......\_xmsgs
...\......\................\......\..........\....\.......\__projnav.log
...\......\................\......\..........\....\README.txt
...\......\................\......\..........\....\synthesis
...\......\................\......\..........\....\.........\ip_xst.prj
...\......\................\......\..........\....\.........\ip_xst.scr
...\......\................\......\..........\hdl
...\......\................\......\..........\...\vhdl
...\......\................\......\..........\...\....\ip.vhd
...\......\................\......\..........\...\....\transcript
...\......\................\......\..........\...\....\user_logic.vhd
...\__xps
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