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systolic

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 2.44mb
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  • Author :che***
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Introduction - If you have any usage issues, please Google them yourself
Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier
Packet file list
(Preview for download)
systolic
........\chains
........\......\demo_16_16.rar
........\......\demo_2_8.rar
........\......\demo_32_8.rar
........\......\demo_8_32.rar
........\......\top.rar
........\charts
........\......\array.vsd
........\......\systolic.vsd
........\......\绘图1.vsd
........\multi
........\.....\and_2_8.v
........\.....\and_xor_7.v
........\.....\and_xor_7.v.bak
........\.....\Block16s.v.bak
........\.....\Block2.v.bak
........\.....\Block3.cr.mti
........\.....\Block3.mpf
........\.....\Block3.v.bak
........\.....\Block32.v
........\.....\Block32.v.bak
........\.....\Block32s.v
........\.....\Block32s.v.bak
........\.....\Block32_1.cr.mti
........\.....\Block32_1.mpf
........\.....\Block4.v.bak
........\.....\Block8.v
........\.....\Block8.v.bak
........\.....\Block8s.v
........\.....\Block8_2.v.bak
........\.....\block8_systolic.v
........\.....\block8_systolic.v.bak
........\.....\Block8_test_version.v
........\.....\Block8_test_version.v.bak
........\.....\Block8_test_version2.v
........\.....\Block8_test_version2.v.bak
........\.....\cell2.v
........\.....\cell2.v.bak
........\.....\cell3.v
........\.....\cell3.v.bak
........\.....\cell4.v
........\.....\cell4.v.bak
........\.....\demo_16_16
........\.....\..........\and_2_16.v
........\.....\..........\and_2_16.v.bak
........\.....\..........\and_xor_15.v
........\.....\..........\and_xor_15.v.bak
........\.....\..........\Block16s.v
........\.....\..........\Block16s.v.bak
........\.....\..........\block16_systolic.v
........\.....\..........\block16_systolic.v.bak
........\.....\..........\cell2.v
........\.....\..........\cell3.v
........\.....\..........\cell4.v
........\.....\..........\demo_16_16.cr.mti
........\.....\..........\demo_16_16.mpf
........\.....\..........\mux_2.v
........\.....\..........\op16.v
........\.....\..........\op16.v.bak
........\.....\..........\transcript
........\.....\..........\work
........\.....\..........\....\@block16s
........\.....\..........\....\.........\verilog.asm
........\.....\..........\....\.........\_primary.dat
........\.....\..........\....\.........\_primary.vhd
........\.....\..........\....\@block8s
........\.....\..........\....\........\verilog.asm
........\.....\..........\....\........\_primary.dat
........\.....\..........\....\........\_primary.vhd
........\.....\..........\....\and_2_8
........\.....\..........\....\.......\verilog.asm
........\.....\..........\....\.......\_primary.dat
........\.....\..........\....\.......\_primary.vhd
........\.....\..........\....\and_xor_15
........\.....\..........\....\..........\verilog.asm
........\.....\..........\....\..........\_primary.dat
........\.....\..........\....\..........\_primary.vhd
........\.....\..........\....\cell2
........\.....\..........\....\.....\verilog.asm
........\.....\..........\....\.....\_primary.dat
........\.....\..........\....\.....\_primary.vhd
........\.....\..........\....\cell3
........\.....\..........\....\.....\verilog.asm
........\.....\..........\....\.....\_primary.dat
........\.....\..........\....\.....\_primary.vhd
........\.....\..........\....\cell4
........\.....\..........\....\.....\verilog.asm
........\.....\..........\....\.....\_primary.dat
........\.....\..........\....\.....\_primary.vhd
........\.....\..........\....\mux_2
........\.....\..........\....\.....\verilog.asm
........\.....\..........\....\.....\_primary.dat
........\.....\..........\....\.....\_primary.vhd
........\.....\..........\....\sys_block_16
........\.....\..........\....\............\verilog.asm
........\.....\..........\....\............\_primary.dat
........\.....\..........\....\............\_primary.vhd
........\.....\..........\....\_info
........\.....\demo_2_8
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