FPGA using VHDL written FSK procedures, control of a flexible, complete works

FSK
...\db
...\..\FSK.asm.qmsg
...\..\FSK.asm_labs.ddb
...\..\FSK.cbx.xml
...\..\FSK.cmp.bpm
...\..\FSK.cmp.cdb
...\..\FSK.cmp.ecobp
...\..\FSK.cmp.hdb
...\..\FSK.cmp.logdb
...\..\FSK.cmp.rdb
...\..\FSK.cmp.tdb
...\..\FSK.cmp0.ddb
...\..\FSK.cmp2.ddb
...\..\FSK.cmp_bb.cdb
...\..\FSK.cmp_bb.hdb
...\..\FSK.cmp_bb.logdb
...\..\FSK.cmp_bb.rcf
...\..\FSK.dbp
...\..\FSK.db_info
...\..\FSK.eco.cdb
...\..\FSK.fit.qmsg
...\..\FSK.hier_info
...\..\FSK.hif
...\..\FSK.map.bpm
...\..\FSK.map.cdb
...\..\FSK.map.ecobp
...\..\FSK.map.hdb
...\..\FSK.map.logdb
...\..\FSK.map.qmsg
...\..\FSK.map_bb.cdb
...\..\FSK.map_bb.hdb
...\..\FSK.map_bb.logdb
...\..\FSK.pre_map.cdb
...\..\FSK.pre_map.hdb
...\..\FSK.psp
...\..\FSK.pss
...\..\FSK.rtlv.hdb
...\..\FSK.rtlv_sg.cdb
...\..\FSK.rtlv_sg_swap.cdb
...\..\FSK.sgdiff.cdb
...\..\FSK.sgdiff.hdb
...\..\FSK.signalprobe.cdb
...\..\FSK.sld_design_entry.sci
...\..\FSK.sld_design_entry_dsc.sci
...\..\FSK.syn_hier_info
...\..\FSK.tan.qmsg
...\..\FSK.tis_db_list.ddb
...\..\prev_cmp_FSK.qmsg
...\FSK.asm.rpt
...\FSK.bdf
...\FSK.done
...\FSK.fit.rpt
...\FSK.fit.smsg
...\FSK.fit.summary
...\FSK.flow.rpt
...\FSK.map.rpt
...\FSK.map.summary
...\FSK.pin
...\FSK.pof
...\FSK.qpf
...\FSK.qsf
...\FSK.qws
...\FSK.sof
...\FSK.tan.rpt
...\FSK.tan.summary
...\PL_FSK.bsf
...\PL_FSK.vhd
...\PL_FSK.vhd.bak
...\PL_FSK2.bsf
...\PL_FSK2.vhd
...\PL_FSK2.vhd.bak

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