Verilog language used to achieve a common decoder 3-8.

Decoder_3_8
...........\cmp_state.ini
...........\db
...........\..\Decoder_3_8.asm.qmsg
...........\..\Decoder_3_8.cmp.cdb
...........\..\Decoder_3_8.cmp.ddb
...........\..\Decoder_3_8.cmp.hdb
...........\..\Decoder_3_8.cmp.rdb
...........\..\Decoder_3_8.cmp.tdb
...........\..\Decoder_3_8.cmp0.ddb
...........\..\Decoder_3_8.db_info
...........\..\Decoder_3_8.eco.cdb
...........\..\Decoder_3_8.eds_overflow
...........\..\Decoder_3_8.fit.qmsg
...........\..\Decoder_3_8.hier_info
...........\..\Decoder_3_8.hif
...........\..\Decoder_3_8.map.cdb
...........\..\Decoder_3_8.map.hdb
...........\..\Decoder_3_8.map.qmsg
...........\..\Decoder_3_8.pre_map.cdb
...........\..\Decoder_3_8.pre_map.hdb
...........\..\Decoder_3_8.psp
...........\..\Decoder_3_8.rtlv.hdb
...........\..\Decoder_3_8.rtlv_sg.cdb
...........\..\Decoder_3_8.rtlv_sg_swap.cdb
...........\..\Decoder_3_8.sgdiff.cdb
...........\..\Decoder_3_8.sgdiff.hdb
...........\..\Decoder_3_8.sim.hdb
...........\..\Decoder_3_8.sim.qmsg
...........\..\Decoder_3_8.sim.rdb
...........\..\Decoder_3_8.sim.vwf
...........\..\Decoder_3_8.sld_design_entry.sci
...........\..\Decoder_3_8.sld_design_entry_dsc.sci
...........\..\Decoder_3_8.syn_hier_info
...........\..\Decoder_3_8.tan.qmsg
...........\..\Decoder_3_8_cmp.qrpt
...........\..\Decoder_3_8_sim.qrpt
...........\Decoder_3_8.asm.rpt
...........\Decoder_3_8.done
...........\Decoder_3_8.fit.eqn
...........\Decoder_3_8.fit.rpt
...........\Decoder_3_8.fit.summary
...........\Decoder_3_8.flow.rpt
...........\Decoder_3_8.map.eqn
...........\Decoder_3_8.map.rpt
...........\Decoder_3_8.map.summary
...........\Decoder_3_8.pin
...........\Decoder_3_8.pof
...........\Decoder_3_8.qpf
...........\Decoder_3_8.qsf
...........\Decoder_3_8.qws
...........\Decoder_3_8.sim.rpt
...........\Decoder_3_8.tan.rpt
...........\Decoder_3_8.tan.summary
...........\Decoder_3_8.v
...........\Decoder_3_8.vwf

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