Verilog language used to achieve the full adder can be integrated to simulation through

Full_Adder
..........\cmp_state.ini
..........\db
..........\..\Full_Adder.asm.qmsg
..........\..\Full_Adder.cmp.cdb
..........\..\Full_Adder.cmp.ddb
..........\..\Full_Adder.cmp.hdb
..........\..\Full_Adder.cmp.rdb
..........\..\Full_Adder.cmp.tdb
..........\..\Full_Adder.cmp0.ddb
..........\..\Full_Adder.db_info
..........\..\Full_Adder.eco.cdb
..........\..\Full_Adder.eds_overflow
..........\..\Full_Adder.fit.qmsg
..........\..\Full_Adder.hier_info
..........\..\Full_Adder.hif
..........\..\Full_Adder.map.cdb
..........\..\Full_Adder.map.hdb
..........\..\Full_Adder.map.qmsg
..........\..\Full_Adder.pre_map.cdb
..........\..\Full_Adder.pre_map.hdb
..........\..\Full_Adder.psp
..........\..\Full_Adder.rtlv.hdb
..........\..\Full_Adder.rtlv_sg.cdb
..........\..\Full_Adder.rtlv_sg_swap.cdb
..........\..\Full_Adder.sgdiff.cdb
..........\..\Full_Adder.sgdiff.hdb
..........\..\Full_Adder.sim.hdb
..........\..\Full_Adder.sim.qmsg
..........\..\Full_Adder.sim.rdb
..........\..\Full_Adder.sim.vwf
..........\..\Full_Adder.sld_design_entry.sci
..........\..\Full_Adder.sld_design_entry_dsc.sci
..........\..\Full_Adder.syn_hier_info
..........\..\Full_Adder.tan.qmsg
..........\..\Full_Adder_cmp.qrpt
..........\..\Full_Adder_sim.qrpt
..........\Full_Adder.asm.rpt
..........\Full_Adder.done
..........\Full_Adder.fit.eqn
..........\Full_Adder.fit.rpt
..........\Full_Adder.fit.summary
..........\Full_Adder.flow.rpt
..........\Full_Adder.map.eqn
..........\Full_Adder.map.rpt
..........\Full_Adder.map.summary
..........\Full_Adder.pin
..........\Full_Adder.pof
..........\Full_Adder.qpf
..........\Full_Adder.qsf
..........\Full_Adder.qws
..........\Full_Adder.sim.rpt
..........\Full_Adder.tan.rpt
..........\Full_Adder.tan.summary
..........\Full_Adder.v
..........\Full_Adder.vwf

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