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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 223kb
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  • Author :杨****
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Introduction - If you have any usage issues, please Google them yourself
To do their own development board, based on the control epm7064slc44-10 digital tube display 0-F. Help beginners to learn.
Packet file list
(Preview for download)
seg
...\cmp_state.ini
...\db
...\..\add_sub_6ph.tdf
...\..\add_sub_onh.tdf
...\..\seg.asm.qmsg
...\..\seg.cmp.cdb
...\..\seg.cmp.ddb
...\..\seg.cmp.hdb
...\..\seg.cmp.rdb
...\..\seg.cmp.tdb
...\..\seg.cmp0.ddb
...\..\seg.db_info
...\..\seg.eco.cdb
...\..\seg.eds_overflow
...\..\seg.fit.qmsg
...\..\seg.frm.hdb
...\..\seg.hier_info
...\..\seg.hif
...\..\seg.map.cdb
...\..\seg.map.hdb
...\..\seg.map.qmsg
...\..\seg.pre_map.cdb
...\..\seg.pre_map.hdb
...\..\seg.psp
...\..\seg.rtlv.hdb
...\..\seg.rtlv_sg.cdb
...\..\seg.rtlv_sg_swap.cdb
...\..\seg.sgdiff.cdb
...\..\seg.sgdiff.hdb
...\..\seg.sim.hdb
...\..\seg.sim.qmsg
...\..\seg.sim.rdb
...\..\seg.sim.vwf
...\..\seg.sld_design_entry.sci
...\..\seg.sld_design_entry_dsc.sci
...\..\seg.swb.qmsg
...\..\seg.syn_hier_info
...\..\seg.tan.qmsg
...\..\seg_cmp.qrpt
...\..\seg_sim.qrpt
...\seg.asm.rpt
...\seg.done
...\seg.fit.eqn
...\seg.fit.rpt
...\seg.fit.summary
...\seg.flow.rpt
...\seg.map.eqn
...\seg.map.rpt
...\seg.map.summary
...\seg.pin
...\seg.pof
...\seg.qpf
...\seg.qsf
...\seg.qws
...\seg.sim.rpt
...\seg.tan.rpt
...\seg.tan.summary
...\seg.vhd
...\seg.vwf
...\参数参照表.txt
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