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UP3_CLOCK

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 711kb
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  • Author :ke***
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Introduction - If you have any usage issues, please Google them yourself
In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified.
Packet file list
(Preview for download)
实验5-时钟设计-1
................\db
................\..\add_sub_4rh.tdf
................\..\add_sub_8rh.tdf
................\..\add_sub_ish.tdf
................\..\add_sub_osh.tdf
................\..\UP3_CLOCK.asm.qmsg
................\..\UP3_CLOCK.cbx.xml
................\..\UP3_CLOCK.cmp.cdb
................\..\UP3_CLOCK.cmp.hdb
................\..\UP3_CLOCK.cmp.kpt
................\..\UP3_CLOCK.cmp.logdb
................\..\UP3_CLOCK.cmp.rdb
................\..\UP3_CLOCK.cmp.tdb
................\..\UP3_CLOCK.cmp0.ddb
................\..\UP3_CLOCK.dbp
................\..\UP3_CLOCK.db_info
................\..\UP3_CLOCK.eco.cdb
................\..\UP3_CLOCK.eds_overflow
................\..\UP3_CLOCK.fit.qmsg
................\..\UP3_CLOCK.fnsim.hdb
................\..\UP3_CLOCK.fnsim.qmsg
................\..\UP3_CLOCK.hier_info
................\..\UP3_CLOCK.hif
................\..\UP3_CLOCK.map.cdb
................\..\UP3_CLOCK.map.hdb
................\..\UP3_CLOCK.map.logdb
................\..\UP3_CLOCK.map.qmsg
................\..\UP3_CLOCK.pre_map.cdb
................\..\UP3_CLOCK.pre_map.hdb
................\..\UP3_CLOCK.psp
................\..\UP3_CLOCK.rtlv.hdb
................\..\UP3_CLOCK.rtlv_sg.cdb
................\..\UP3_CLOCK.rtlv_sg_swap.cdb
................\..\UP3_CLOCK.sgdiff.cdb
................\..\UP3_CLOCK.sgdiff.hdb
................\..\UP3_CLOCK.signalprobe.cdb
................\..\UP3_CLOCK.sim.hdb
................\..\UP3_CLOCK.sim.qmsg
................\..\UP3_CLOCK.sim.rdb
................\..\UP3_CLOCK.sim_ori.vwf
................\..\UP3_CLOCK.sld_design_entry.sci
................\..\UP3_CLOCK.sld_design_entry_dsc.sci
................\..\UP3_CLOCK.smp_dump.txt
................\..\UP3_CLOCK.syn_hier_info
................\..\UP3_CLOCK.tan.qmsg
................\..\wed.zsf
................\UP3_CLOCK.asm.rpt
................\UP3_CLOCK.cdf
................\UP3_CLOCK.done
................\UP3_CLOCK.fit.rpt
................\UP3_CLOCK.fit.smsg
................\UP3_CLOCK.fit.summary
................\UP3_CLOCK.flow.rpt
................\UP3_CLOCK.map.rpt
................\UP3_CLOCK.map.summary
................\UP3_CLOCK.pin
................\UP3_CLOCK.pof
................\UP3_CLOCK.qpf
................\UP3_CLOCK.qsf
................\UP3_CLOCK.qws
................\UP3_CLOCK.sim.rpt
................\UP3_CLOCK.sof
................\UP3_CLOCK.tan.rpt
................\UP3_CLOCK.tan.summary
................\UP3_CLOCK.vhd
................\UP3_CLOCK.vwf
................\UP3_CLOCK_assignment_defaults.qdf
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