ddr ram controller vhdl code

ddr_ctrlv
.........\.bzrignore
.........\bench
.........\.....\fml_memtest.v
.........\.....\lac
.........\.....\...\dp_ram.v
.........\.....\...\lac.v
.........\.....\...\uart.v
.........\.....\system.v
.........\rtl
.........\...\async_fifo.v
.........\...\async_fifo.v.bak
.........\...\ddr_clkgen.v
.........\...\ddr_ctrl.v
.........\...\ddr_include.v
.........\...\ddr_init.v
.........\...\ddr_pulse78.v
.........\...\ddr_rpath.v
.........\...\ddr_wpath.v
.........\...\gray_counter.v
.........\...\rotary.v
.........\sim
.........\...\ddr
.........\...\...\ddr.v
.........\...\...\parameters.v
.........\...\...\readme.txt
.........\...\Makefile
.........\...\system_tb.list
.........\...\system_tb.save
.........\...\system_tb.v
.........\...\unisims
.........\...\.......\BUFG.v
.........\...\.......\DCM_SP.v
.........\...\.......\FDDRRSE.v
.........\syn
.........\...\Makefile
.........\...\system.prj
.........\...\system.ucf
.........\...\system.xst

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