Verilog language in maxII series chip IIC function

i2c
...\.xhdl3.xref
...\cmp_state.ini
...\db
...\..\add_sub_5ph.tdf
...\..\add_sub_6ph.tdf
...\..\add_sub_dph.tdf
...\..\add_sub_rnh.tdf
...\..\i2c.asm.qmsg
...\..\i2c.asm_labs.ddb
...\..\i2c.cbx.xml
...\..\i2c.cmp.cdb
...\..\i2c.cmp.hdb
...\..\i2c.cmp.qrpt
...\..\i2c.cmp.rdb
...\..\i2c.cmp.tdb
...\..\i2c.cmp0.ddb
...\..\i2c.dbp
...\..\i2c.db_info
...\..\i2c.eco.cdb
...\..\i2c.fit.qmsg
...\..\i2c.hier_info
...\..\i2c.hif
...\..\i2c.map.cdb
...\..\i2c.map.hdb
...\..\i2c.map.qmsg
...\..\i2c.pre_map.cdb
...\..\i2c.pre_map.hdb
...\..\i2c.psp
...\..\i2c.rtlv.hdb
...\..\i2c.rtlv_sg.cdb
...\..\i2c.rtlv_sg_swap.cdb
...\..\i2c.sgdiff.cdb
...\..\i2c.sgdiff.hdb
...\..\i2c.signalprobe.cdb
...\..\i2c.sld_design_entry.sci
...\..\i2c.sld_design_entry_dsc.sci
...\..\i2c.smp_dump.txt
...\..\i2c.syn_hier_info
...\..\i2c.tan.qmsg
...\..\i2c_cmp.qrpt
...\i2c.asm.rpt
...\i2c.cdf
...\i2c.done
...\i2c.fit.eqn
...\i2c.fit.rpt
...\i2c.fit.summary
...\i2c.flow.rpt
...\i2c.map.eqn
...\i2c.map.rpt
...\i2c.map.summary
...\i2c.pin
...\i2c.pof
...\i2c.qpf
...\i2c.qsf
...\i2c.qws
...\i2c.tan.rpt
...\i2c.tan.summary
...\i2c.v
...\i2c.v.bak
...\i2c_assignment_defaults.qdf
...\serv_req_info.txt

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