crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.

crc16_ccitt
...........\CRC16_D8_m.v
...........\CRC16_D8_m_tb.v
...........\crc_table.c
...........\crc_table_1.c

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