VHDL language used to develop a 16 with five lines of the CPU design

CPU16
.....\cache.vhd
.....\CPU16.ise
.....\CPU16.ise_ISE_Backup
.....\CPU16.ntrc_log
.....\four.vhd
.....\kernel.vhd
.....\kernel_summary.html
.....\mem1.asy
.....\mem1.ngc
.....\mem1.sym
.....\mem1.v
.....\mem1.veo
.....\mem1.vhd
.....\mem1.vho
.....\mem1.xco
.....\mem1_flist.txt
.....\mem1_readme.txt
.....\mem1_xmdf.tcl
.....\memory.asy
.....\memory.ngc
.....\memory.sym
.....\memory.v
.....\memory.veo
.....\memory.vhd
.....\memory.vho
.....\memory.xco
.....\memory_flist.txt
.....\memory_readme.txt
.....\memory_xmdf.tcl
.....\templates
.....\.........\coregen.xml
.....\tmp
.....\...\_cg
.....\top.bld
.....\top.cmd_log
.....\top.lso
.....\top.ncd
.....\top.ngc
.....\top.ngd
.....\top.ngr
.....\top.pad
.....\top.par
.....\top.pcf
.....\top.prj
.....\top.stx
.....\top.syr
.....\top.twr
.....\top.twx
.....\top.unroutes
.....\top.vhd
.....\top.xpi
.....\top.xst
.....\top_guide.ncd
.....\top_map.map
.....\top_map.mrp
.....\top_map.ncd
.....\top_map.ngm
.....\top_pad.csv
.....\top_pad.txt
.....\top_summary.html
.....\top_summary.xml
.....\top_usage.xml
.....\top_vhdl.prj
.....\xst
.....\...\dump.xst
.....\...\........\top.prj
.....\...\........\.......\ngx
.....\...\........\.......\...\notopt
.....\...\........\.......\...\opt
.....\...\file graph
.....\...\projnav.tmp
.....\...\work
.....\...\....\hdllib.ref
.....\...\....\hdpdeps.ref
.....\...\....\sub00
.....\...\....\.....\vhpl00.vho
.....\...\....\.....\vhpl01.vho
.....\...\....\.....\vhpl02.vho
.....\...\....\.....\vhpl03.vho
.....\...\....\.....\vhpl04.vho
.....\...\....\.....\vhpl05.vho
.....\...\....\.....\vhpl06.vho
.....\...\....\.....\vhpl07.vho
.....\...\....\.....\vhpl08.vho
.....\...\....\.....\vhpl09.vho
.....\...\....\.....\vhpl10.vho
.....\...\....\.....\vhpl11.vho
.....\_ngo
.....\....\netlist.lst
.....\_xmsgs
.....\......\map.xmsgs
.....\......\ngdbuild.xmsgs
.....\......\par.xmsgs
.....\......\trce.xmsgs
.....\......\xst.xmsgs

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