Verilog 43 of the actual use cases for the general learning and developers to learn and practice. Understanding of Verilog hardware description language, there are a great help.

图像所verilog实例 【46】
........................\ADC_16bit.v
........................\adder_8bit.v
........................\adder_8bit_2.v
........................\ALL.V
........................\binarytogray.v
........................\cla_8bits.v
........................\COMPARE.V
........................\dds.v
........................\DECODER1.V
........................\decoder3x8.v
........................\div16.v
........................\encoder8x3.v
........................\encoder8x3_2.v
........................\fifo.v
........................\fifo_16x16.v
........................\FIFO_2.V
........................\framer.v
........................\frequency5x2.v
........................\full_adder_1.v
........................\full_adder_2.v
........................\gencrc.v.txt
........................\half_adder_1.v
........................\half_adder_2.v
........................\half_adder_3.v
........................\lead_8bits_adder.v
........................\lead_8bits_adder2.v
........................\MUL16.V
........................\mult16.v
........................\multi_select_1.v
........................\mult_piped_8x8.v
........................\mult_select.v
........................\MUX8X8.V
........................\myrand.c
........................\nco.v
........................\onehot.v
........................\pic.v
........................\PLI.TAR
........................\RISC8.ZIP
........................\sequence_dectect.v
........................\SHIFTER.V
........................\string.v
........................\SYNTHPIC.ZIP
........................\TEST.V
........................\testing.v.txt
........................\test_cla_8bits.v
........................\wpulse.v.txt

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