A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.

ARelativelySimpleRISCCPU
........................\risc_cpu
........................\........\ datactl.v
........................\........\accum.v
........................\........\addr_decode.v
........................\........\adr.v
........................\........\alu.v
........................\........\clk_gen.v
........................\........\counter.v
........................\........\cpu_top.v
........................\........\datactl.v
........................\........\machine.v
........................\........\machinectl.v
........................\........\ram.v
........................\........\register.v
........................\........\Risc_cpu设计说明文档.doc
........................\........\rom.v
........................\........\test_cpu.v

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