The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm, such as finite field multiplication algorithm has requested

xor_mul
.......\cmp_state.ini
.......\db
.......\..\xor_mul.asm.qmsg
.......\..\xor_mul.cbx.xml
.......\..\xor_mul.cmp.cdb
.......\..\xor_mul.cmp.hdb
.......\..\xor_mul.cmp.rdb
.......\..\xor_mul.cmp.tdb
.......\..\xor_mul.cmp0.ddb
.......\..\xor_mul.db_info
.......\..\xor_mul.eco.cdb
.......\..\xor_mul.eds_overflow
.......\..\xor_mul.fit.qmsg
.......\..\xor_mul.fnsim.hdb
.......\..\xor_mul.hier_info
.......\..\xor_mul.hif
.......\..\xor_mul.map.cdb
.......\..\xor_mul.map.hdb
.......\..\xor_mul.map.qmsg
.......\..\xor_mul.pre_map.cdb
.......\..\xor_mul.pre_map.hdb
.......\..\xor_mul.psp
.......\..\xor_mul.rpp.qmsg
.......\..\xor_mul.rtlv.hdb
.......\..\xor_mul.rtlv_sg.cdb
.......\..\xor_mul.rtlv_sg_swap.cdb
.......\..\xor_mul.sgate.rvd
.......\..\xor_mul.sgdiff.cdb
.......\..\xor_mul.sgdiff.hdb
.......\..\xor_mul.signalprobe.cdb
.......\..\xor_mul.sim.hdb
.......\..\xor_mul.sim.qmsg
.......\..\xor_mul.sim.rdb
.......\..\xor_mul.sim.vwf
.......\..\xor_mul.sld_design_entry.sci
.......\..\xor_mul.sld_design_entry_dsc.sci
.......\..\xor_mul.syn_hier_info
.......\..\xor_mul.tan.qmsg
.......\..\xor_mul_cmp.qrpt
.......\..\xor_mul_sim.qrpt
.......\xor_mul.asm.rpt
.......\xor_mul.done
.......\xor_mul.fit.eqn
.......\xor_mul.fit.rpt
.......\xor_mul.fit.summary
.......\xor_mul.flow.rpt
.......\xor_mul.map.eqn
.......\xor_mul.map.rpt
.......\xor_mul.map.summary
.......\xor_mul.pin
.......\xor_mul.pof
.......\xor_mul.qpf
.......\xor_mul.qsf
.......\xor_mul.qws
.......\xor_mul.sim.rpt
.......\xor_mul.sof
.......\xor_mul.tan.rpt
.......\xor_mul.tan.summary
.......\xor_mul.vhd
.......\xor_mul.vwf

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