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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 359kb
  • Downloaded :0次
  • Author :长***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Cyclic Redundancy Check realize Verilog source code
Packet file list
(Preview for download)
FilenameSizeUpdate
CRC(73)
........\CRC(73).ise
........\CRC(73).ise_ISE_Backup
........\CRC(73).ntrc_log
........\crc73.bld
........\crc73.cmd_log
........\crc73.lso
........\crc73.ncd
........\crc73.ngc
........\crc73.ngd
........\crc73.ngr
........\crc73.pad
........\crc73.par
........\crc73.pcf
........\crc73.prj
........\crc73.stx
........\crc73.syr
........\crc73.twr
........\crc73.twx
........\crc73.unroutes
........\crc73.v
........\crc73.xpi
........\crc73.xst
........\crc73_dc.v
........\crc73_guide.ncd
........\crc73_map.map
........\crc73_map.mrp
........\crc73_map.ncd
........\crc73_map.ngm
........\crc73_pad.csv
........\crc73_pad.txt
........\crc73_prev_built.ngd
........\crc73_summary.html
........\crc73_summary.xml
........\crc73_top.bld
........\crc73_top.cmd_log
........\crc73_top.lso
........\crc73_top.ngc
........\crc73_top.ngr
........\crc73_top.prj
........\crc73_top.stx
........\crc73_top.syr
........\crc73_top.v
........\crc73_top.xst
........\crc73_top_summary.html
........\crc73_usage.xml
........\netgen
........\......\par
........\......\...\crc73_timesim.nlf
........\......\...\crc73_timesim.sdf
........\......\...\crc73_timesim.v
........\test.v
........\test_top.v
........\test_top_v.fdo
........\test_top_v.udo
........\test_v.fdo
........\test_v.tdo
........\test_v.udo
........\transcript
........\vsim.wlf
........\work
........\....\crc73
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\crc73_dc
........\....\........\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\crc73_top
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\glbl
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\test_top_v
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\test_v
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\_info
........\....\_temp
........\xst
........\...\dump.xst
........\...\........\crc73.prj
........\...\........\.........\ngx
........\...\........\.........\...\notopt
........\...\........\.........\...\opt
........\...\........\.........\ntrc.scr
........\...\........\crc73_top.prj
........\...\........\.............\ngx
........\...\........\.............\...\notopt
........\...\........\.............\...\opt
........\...\........\.............\ntrc.scr
........\...\projnav.tmp
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