FPGA platform for voice communications design example Oh

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..\aclink2.vhd
..\aclink3.vhd
..\ad.vhd
..\cdeled10.vhd
..\clk.vhd
..\comm_buff.bdf
..\constant.vhd
..\CONSTANT_inst.vhd
..\csout.vhd
..\decoder1.vhd
..\DFF.vhd
..\DFF_1.vhd
..\DFF_1_inst.vhd
..\dff_8.vhd
..\DFF_81.vhd
..\DFF_81_inst.vhd
..\dff_8_inst.vhd
..\DFF_inst.vhd
..\divider.vhd
..\division.vhd
..\division1.vhd
..\div_sheng.vhd
..\fbc.bdf
..\fbc_rom.vhd
..\fbc_rom_inst.vhd
..\fc.vhd
..\filter.bdf
..\g8k.bdf
..\L1.vhd
..\L1_inst.vhd
..\lpm_constana.vhd
..\LPM_CONSTANa_inst.vhd
..\mul2wr.vhd
..\mul3.vhd
..\mux2_1.vhd
..\mux8_2.vhd
..\paly_buff.bdf
..\playwave.bdf
..\playwave1.bdf
..\receive.cpp
..\rxcver.vhd
..\rxt.vhd
..\send.cpp
..\Speaker.vhd
..\sreg1.vhd
..\sreg3.vhd
..\terminal_count.vhd
..\test.bdf
..\testda.vhd
..\testg8k.bdf
..\tff_1.bdf
..\TFF_1.vhd
..\TFF_1_inst.vhd
..\Tone.vhd
..\tone2.vhd
..\TOP.vhd
..\txmit.vhd
..\txmittest.vhd
..\uart.vhd

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