FPGA signal modulation communication system design example

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..\aaf.mif
..\addr.vhd
..\addr_a_f.vhd
..\add_a_f.vhd
..\asin.mif
..\dis_sig.vhd
..\division10.vhd
..\division4.vhd
..\drive.vhd
..\fangbo.vhd
..\fpdpsk.vhd
..\key.bdf
..\key1.vhd
..\lut.vhd
..\lut_a_f.vhd
..\Result.vhd
..\Result_inst.vhd
..\rsnand.vhd
..\sanjiao.vhd
..\sel2.vhd
..\selampl.vhd
..\sel_ampl.vhd
..\show.vhd
..\test.vhd
..\testrom.vhd
..\testrom_inst.vhd
..\testup.bdf
..\testup_f_k.bdf
..\test_inst.vhd
..\updown.vhd
..\updown2.vhd
..\wavgenerator.bdf
..\wavgenerator1.pin

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